c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
326 lines
11 KiB
Systemverilog
326 lines
11 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_fpu_define.vh"
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`ifdef FPU_DSP
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module VX_fpu_dsp import VX_fpu_pkg::*; #(
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parameter NUM_LANES = 4,
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parameter TAGW = 4,
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parameter OUT_REG = 0
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) (
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input wire clk,
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input wire reset,
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input wire valid_in,
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output wire ready_in,
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input wire [NUM_LANES-1:0] lane_mask,
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input wire [TAGW-1:0] tag_in,
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input wire [`INST_FPU_BITS-1:0] op_type,
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input wire [`INST_FMT_BITS-1:0] fmt,
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input wire [`INST_FRM_BITS-1:0] frm,
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input wire [NUM_LANES-1:0][`XLEN-1:0] dataa,
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input wire [NUM_LANES-1:0][`XLEN-1:0] datab,
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input wire [NUM_LANES-1:0][`XLEN-1:0] datac,
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output wire [NUM_LANES-1:0][`XLEN-1:0] result,
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output wire has_fflags,
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output wire [`FP_FLAGS_BITS-1:0] fflags,
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output wire [TAGW-1:0] tag_out,
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input wire ready_out,
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output wire valid_out
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);
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localparam FPU_FMA = 0;
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localparam FPU_DIVSQRT = 1;
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localparam FPU_CVT = 2;
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localparam FPU_NCP = 3;
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localparam NUM_FPC = 4;
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localparam FPC_BITS = `LOG2UP(NUM_FPC);
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localparam RSP_DATAW = (NUM_LANES * 32) + 1 + $bits(fflags_t) + TAGW;
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`UNUSED_VAR (fmt)
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wire [NUM_FPC-1:0] per_core_ready_in;
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wire [NUM_FPC-1:0][NUM_LANES-1:0][31:0] per_core_result;
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wire [NUM_FPC-1:0][TAGW-1:0] per_core_tag_out;
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wire [NUM_FPC-1:0] per_core_ready_out;
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wire [NUM_FPC-1:0] per_core_valid_out;
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wire [NUM_FPC-1:0] per_core_has_fflags;
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fflags_t [NUM_FPC-1:0] per_core_fflags;
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wire div_ready_in, sqrt_ready_in;
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wire [NUM_LANES-1:0][31:0] div_result, sqrt_result;
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wire [TAGW-1:0] div_tag_out, sqrt_tag_out;
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wire div_ready_out, sqrt_ready_out;
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wire div_valid_out, sqrt_valid_out;
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wire div_has_fflags, sqrt_has_fflags;
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fflags_t div_fflags, sqrt_fflags;
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reg [FPC_BITS-1:0] core_select;
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reg is_madd, is_sub, is_neg, is_div, is_itof, is_signed;
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always @(*) begin
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is_madd = 0;
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is_sub = 0;
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is_neg = 0;
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is_div = 0;
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is_itof = 0;
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is_signed = 0;
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case (op_type)
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`INST_FPU_ADD: begin core_select = FPU_FMA; end
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`INST_FPU_SUB: begin core_select = FPU_FMA; is_sub = 1; end
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`INST_FPU_MUL: begin core_select = FPU_FMA; is_neg = 1; end
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`INST_FPU_MADD: begin core_select = FPU_FMA; is_madd = 1; end
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`INST_FPU_MSUB: begin core_select = FPU_FMA; is_madd = 1; is_sub = 1; end
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`INST_FPU_NMADD: begin core_select = FPU_FMA; is_madd = 1; is_neg = 1; end
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`INST_FPU_NMSUB: begin core_select = FPU_FMA; is_madd = 1; is_sub = 1; is_neg = 1; end
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`INST_FPU_DIV: begin core_select = FPU_DIVSQRT; is_div = 1; end
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`INST_FPU_SQRT: begin core_select = FPU_DIVSQRT; end
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`INST_FPU_F2I: begin core_select = FPU_CVT; is_signed = 1; end
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`INST_FPU_F2U: begin core_select = FPU_CVT; end
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`INST_FPU_I2F: begin core_select = FPU_CVT; is_itof = 1; is_signed = 1; end
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`INST_FPU_U2F: begin core_select = FPU_CVT; is_itof = 1; end
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default: begin core_select = FPU_NCP; end
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endcase
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end
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`RESET_RELAY (fma_reset, reset);
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`RESET_RELAY (div_reset, reset);
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`RESET_RELAY (sqrt_reset, reset);
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`RESET_RELAY (cvt_reset, reset);
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`RESET_RELAY (ncp_reset, reset);
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wire [NUM_LANES-1:0][31:0] dataa_s;
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wire [NUM_LANES-1:0][31:0] datab_s;
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wire [NUM_LANES-1:0][31:0] datac_s;
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for (genvar i = 0; i < NUM_LANES; ++i) begin
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assign dataa_s[i] = dataa[i][31:0];
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assign datab_s[i] = datab[i][31:0];
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assign datac_s[i] = datac[i][31:0];
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end
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`UNUSED_VAR (dataa)
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`UNUSED_VAR (datab)
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`UNUSED_VAR (datac)
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VX_fpu_fma #(
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.NUM_LANES (NUM_LANES),
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.TAGW (TAGW)
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) fpu_fma (
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.clk (clk),
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.reset (fma_reset),
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.valid_in (valid_in && (core_select == FPU_FMA)),
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.ready_in (per_core_ready_in[FPU_FMA]),
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.lane_mask (lane_mask),
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.tag_in (tag_in),
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.frm (frm),
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.is_madd (is_madd),
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.is_sub (is_sub),
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.is_neg (is_neg),
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.dataa (dataa_s),
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.datab (datab_s),
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.datac (datac_s),
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.has_fflags (per_core_has_fflags[FPU_FMA]),
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.fflags (per_core_fflags[FPU_FMA]),
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.result (per_core_result[FPU_FMA]),
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.tag_out (per_core_tag_out[FPU_FMA]),
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.ready_out (per_core_ready_out[FPU_FMA]),
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.valid_out (per_core_valid_out[FPU_FMA])
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);
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VX_fpu_div #(
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.NUM_LANES (NUM_LANES),
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.TAGW (TAGW)
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) fpu_div (
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.clk (clk),
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.reset (div_reset),
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.valid_in (valid_in && (core_select == FPU_DIVSQRT) && is_div),
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.ready_in (div_ready_in),
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.lane_mask (lane_mask),
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.tag_in (tag_in),
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.frm (frm),
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.dataa (dataa_s),
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.datab (datab_s),
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.has_fflags (div_has_fflags),
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.fflags (div_fflags),
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.result (div_result),
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.tag_out (div_tag_out),
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.valid_out (div_valid_out),
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.ready_out (div_ready_out)
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);
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VX_fpu_sqrt #(
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.NUM_LANES (NUM_LANES),
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.TAGW (TAGW)
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) fpu_sqrt (
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.clk (clk),
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.reset (sqrt_reset),
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.valid_in (valid_in && (core_select == FPU_DIVSQRT) && ~is_div),
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.ready_in (sqrt_ready_in),
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.lane_mask (lane_mask),
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.tag_in (tag_in),
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.frm (frm),
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.dataa (dataa_s),
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.has_fflags (sqrt_has_fflags),
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.fflags (sqrt_fflags),
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.result (sqrt_result),
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.tag_out (sqrt_tag_out),
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.valid_out (sqrt_valid_out),
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.ready_out (sqrt_ready_out)
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);
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wire cvt_rt_int_in = ~is_itof;
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wire cvt_rt_int_out;
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VX_fpu_cvt #(
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.NUM_LANES (NUM_LANES),
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.TAGW (TAGW+1)
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) fpu_cvt (
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.clk (clk),
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.reset (cvt_reset),
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.valid_in (valid_in && (core_select == FPU_CVT)),
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.ready_in (per_core_ready_in[FPU_CVT]),
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.lane_mask (lane_mask),
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.tag_in ({cvt_rt_int_in, tag_in}),
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.frm (frm),
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.is_itof (is_itof),
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.is_signed (is_signed),
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.dataa (dataa_s),
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.has_fflags (per_core_has_fflags[FPU_CVT]),
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.fflags (per_core_fflags[FPU_CVT]),
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.result (per_core_result[FPU_CVT]),
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.tag_out ({cvt_rt_int_out, per_core_tag_out[FPU_CVT]}),
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.valid_out (per_core_valid_out[FPU_CVT]),
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.ready_out (per_core_ready_out[FPU_CVT])
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);
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wire ncp_rt_int_in = (op_type == `INST_FPU_CMP)
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|| `INST_FPU_IS_CLASS(op_type, frm)
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|| `INST_FPU_IS_MVXW(op_type, frm);
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wire ncp_rt_int_out;
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wire ncp_rt_sext_in = `INST_FPU_IS_MVXW(op_type, frm);
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wire ncp_rt_sext_out;
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VX_fpu_ncomp #(
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.NUM_LANES (NUM_LANES),
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.TAGW (TAGW+2)
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) fpu_ncomp (
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.clk (clk),
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.reset (ncp_reset),
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.valid_in (valid_in && (core_select == FPU_NCP)),
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.ready_in (per_core_ready_in[FPU_NCP]),
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.lane_mask (lane_mask),
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.tag_in ({ncp_rt_sext_in, ncp_rt_int_in, tag_in}),
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.op_type (op_type),
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.frm (frm),
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.dataa (dataa_s),
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.datab (datab_s),
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.result (per_core_result[FPU_NCP]),
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.has_fflags (per_core_has_fflags[FPU_NCP]),
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.fflags (per_core_fflags[FPU_NCP]),
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.tag_out ({ncp_rt_sext_out, ncp_rt_int_out, per_core_tag_out[FPU_NCP]}),
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.valid_out (per_core_valid_out[FPU_NCP]),
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.ready_out (per_core_ready_out[FPU_NCP])
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);
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///////////////////////////////////////////////////////////////////////////
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assign per_core_ready_in[FPU_DIVSQRT] = is_div ? div_ready_in : sqrt_ready_in;
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VX_stream_arb #(
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.NUM_INPUTS (2),
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.DATAW (RSP_DATAW),
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.ARBITER ("R"),
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.OUT_REG (0)
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) div_sqrt_arb (
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.clk (clk),
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.reset (reset),
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.valid_in ({sqrt_valid_out, div_valid_out}),
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.ready_in ({sqrt_ready_out, div_ready_out}),
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.data_in ({{sqrt_result, sqrt_has_fflags, sqrt_fflags, sqrt_tag_out},
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{div_result, div_has_fflags, div_fflags, div_tag_out}}),
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.data_out ({per_core_result[FPU_DIVSQRT], per_core_has_fflags[FPU_DIVSQRT], per_core_fflags[FPU_DIVSQRT], per_core_tag_out[FPU_DIVSQRT]}),
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.valid_out (per_core_valid_out[FPU_DIVSQRT]),
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.ready_out (per_core_ready_out[FPU_DIVSQRT]),
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`UNUSED_PIN (sel_out)
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);
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///////////////////////////////////////////////////////////////////////////
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reg [NUM_FPC-1:0][RSP_DATAW+2-1:0] per_core_data_out;
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always @(*) begin
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for (integer i = 0; i < NUM_FPC; ++i) begin
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per_core_data_out[i][RSP_DATAW+1:2] = {per_core_result[i], per_core_has_fflags[i], per_core_fflags[i], per_core_tag_out[i]};
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per_core_data_out[i][1:0] = '0;
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end
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per_core_data_out[FPU_CVT][1:0] = {1'b1, cvt_rt_int_out};
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per_core_data_out[FPU_NCP][1:0] = {ncp_rt_sext_out, ncp_rt_int_out};
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end
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wire [NUM_LANES-1:0][31:0] result_s;
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wire [1:0] op_rt_int_out;
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VX_stream_arb #(
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.NUM_INPUTS (NUM_FPC),
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.DATAW (RSP_DATAW + 2),
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.ARBITER ("R"),
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.OUT_REG (OUT_REG)
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) rsp_arb (
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.clk (clk),
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.reset (reset),
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.valid_in (per_core_valid_out),
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.ready_in (per_core_ready_out),
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.data_in (per_core_data_out),
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.data_out ({result_s, has_fflags, fflags, tag_out, op_rt_int_out}),
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.valid_out (valid_out),
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.ready_out (ready_out),
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`UNUSED_PIN (sel_out)
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);
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`ifndef FPU_RV64F
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`UNUSED_VAR (op_rt_int_out)
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`endif
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for (genvar i = 0; i < NUM_LANES; ++i) begin
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`ifdef FPU_RV64F
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reg [`XLEN-1:0] result_r;
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always @(*) begin
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case (op_rt_int_out)
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2'b11: result_r = `XLEN'($signed(result_s[i]));
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2'b01: result_r = {32'h00000000, result_s[i]};
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default: result_r = {32'hffffffff, result_s[i]};
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endcase
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end
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assign result[i] = result_r;
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`else
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assign result[i] = result_s[i];
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`endif
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end
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// can accept new request?
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assign ready_in = per_core_ready_in[core_select];
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endmodule
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`endif
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