c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
86 lines
3.4 KiB
Verilog
86 lines
3.4 KiB
Verilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "vortex_afu.vh"
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module vortex_afu #(
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parameter C_S_AXI_CTRL_ADDR_WIDTH = 8,
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parameter C_S_AXI_CTRL_DATA_WIDTH = 32,
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parameter C_M_AXI_MEM_ID_WIDTH = `M_AXI_MEM_ID_WIDTH,
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parameter C_M_AXI_MEM_ADDR_WIDTH = 64,
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parameter C_M_AXI_MEM_DATA_WIDTH = `VX_MEM_DATA_WIDTH
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) (
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// System signals
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input wire ap_clk,
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input wire ap_rst_n,
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// AXI4 master interface
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`REPEAT (`M_AXI_MEM_NUM_BANKS, GEN_AXI_MEM, REPEAT_COMMA),
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// AXI4-Lite slave interface
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input wire s_axi_ctrl_awvalid,
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output wire s_axi_ctrl_awready,
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input wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_awaddr,
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input wire s_axi_ctrl_wvalid,
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output wire s_axi_ctrl_wready,
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input wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_wdata,
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input wire [C_S_AXI_CTRL_DATA_WIDTH/8-1:0] s_axi_ctrl_wstrb,
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input wire s_axi_ctrl_arvalid,
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output wire s_axi_ctrl_arready,
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input wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_araddr,
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output wire s_axi_ctrl_rvalid,
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input wire s_axi_ctrl_rready,
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output wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_rdata,
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output wire [1:0] s_axi_ctrl_rresp,
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output wire s_axi_ctrl_bvalid,
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input wire s_axi_ctrl_bready,
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output wire [1:0] s_axi_ctrl_bresp,
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output wire interrupt
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);
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VX_afu_wrap #(
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.C_S_AXI_CTRL_ADDR_WIDTH (C_S_AXI_CTRL_ADDR_WIDTH),
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.C_S_AXI_CTRL_DATA_WIDTH (C_S_AXI_CTRL_DATA_WIDTH),
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.C_M_AXI_MEM_ID_WIDTH (C_M_AXI_MEM_ID_WIDTH),
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.C_M_AXI_MEM_ADDR_WIDTH (C_M_AXI_MEM_ADDR_WIDTH),
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.C_M_AXI_MEM_DATA_WIDTH (C_M_AXI_MEM_DATA_WIDTH)
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) afu_wrap (
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.ap_clk (ap_clk),
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.ap_rst_n (ap_rst_n),
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`REPEAT (`M_AXI_MEM_NUM_BANKS, AXI_MEM_ARGS, REPEAT_COMMA),
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.s_axi_ctrl_awvalid (s_axi_ctrl_awvalid),
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.s_axi_ctrl_awready (s_axi_ctrl_awready),
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.s_axi_ctrl_awaddr (s_axi_ctrl_awaddr),
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.s_axi_ctrl_wvalid (s_axi_ctrl_wvalid),
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.s_axi_ctrl_wready (s_axi_ctrl_wready),
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.s_axi_ctrl_wdata (s_axi_ctrl_wdata),
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.s_axi_ctrl_wstrb (s_axi_ctrl_wstrb),
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.s_axi_ctrl_arvalid (s_axi_ctrl_arvalid),
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.s_axi_ctrl_arready (s_axi_ctrl_arready),
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.s_axi_ctrl_araddr (s_axi_ctrl_araddr),
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.s_axi_ctrl_rvalid (s_axi_ctrl_rvalid),
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.s_axi_ctrl_rready (s_axi_ctrl_rready),
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.s_axi_ctrl_rdata (s_axi_ctrl_rdata),
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.s_axi_ctrl_rresp (s_axi_ctrl_rresp),
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.s_axi_ctrl_bvalid (s_axi_ctrl_bvalid),
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.s_axi_ctrl_bready (s_axi_ctrl_bready),
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.s_axi_ctrl_bresp (s_axi_ctrl_bresp),
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.interrupt (interrupt)
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);
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endmodule
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