c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
96 lines
2.9 KiB
C++
96 lines
2.9 KiB
C++
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include <simobject.h>
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#include "mem_sim.h"
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namespace vortex {
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class CacheSim : public SimObject<CacheSim> {
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public:
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struct Config {
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bool bypass; // cache bypass
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uint8_t C; // log2 cache size
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uint8_t B; // log2 block size
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uint8_t W; // log2 word size
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uint8_t A; // log2 associativity
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uint8_t addr_width; // word address bits
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uint8_t num_banks; // number of banks
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uint8_t ports_per_bank; // number of ports per bank
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uint8_t num_inputs; // number of inputs
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bool write_through; // is write-through
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bool write_reponse; // enable write response
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uint16_t victim_size; // victim cache size
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uint16_t mshr_size; // MSHR buffer size
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uint8_t latency; // pipeline latency
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};
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struct PerfStats {
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uint64_t reads;
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uint64_t writes;
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uint64_t read_misses;
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uint64_t write_misses;
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uint64_t evictions;
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uint64_t pipeline_stalls;
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uint64_t bank_stalls;
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uint64_t mshr_stalls;
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uint64_t mem_latency;
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PerfStats()
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: reads(0)
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, writes(0)
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, read_misses(0)
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, write_misses(0)
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, evictions(0)
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, pipeline_stalls(0)
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, bank_stalls(0)
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, mshr_stalls(0)
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, mem_latency(0)
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{}
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PerfStats& operator+=(const PerfStats& rhs) {
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this->reads += rhs.reads;
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this->writes += rhs.writes;
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this->read_misses += rhs.read_misses;
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this->write_misses += rhs.write_misses;
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this->evictions += rhs.evictions;
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this->pipeline_stalls += rhs.pipeline_stalls;
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this->bank_stalls += rhs.bank_stalls;
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this->mshr_stalls += rhs.mshr_stalls;
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this->mem_latency += rhs.mem_latency;
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return *this;
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}
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};
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std::vector<SimPort<MemReq>> CoreReqPorts;
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std::vector<SimPort<MemRsp>> CoreRspPorts;
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SimPort<MemReq> MemReqPort;
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SimPort<MemRsp> MemRspPort;
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CacheSim(const SimContext& ctx, const char* name, const Config& config);
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~CacheSim();
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void reset();
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void tick();
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const PerfStats& perf_stats() const;
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private:
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class Impl;
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Impl* impl_;
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};
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} |