82 lines
2.6 KiB
Verilog
82 lines
2.6 KiB
Verilog
`include "VX_define.vh"
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module VX_branch_unit #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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// Inputs
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VX_branch_req_if branch_req_if,
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// Outputs
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VX_branch_ctl_if branch_ctl_if,
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VX_commit_if branch_commit_if
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);
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wire [`NT_BITS-1:0] br_result_index;
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VX_priority_encoder #(
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.N(`NUM_THREADS)
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) choose_alu_result (
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.data_in (branch_req_if.valid),
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.data_out (br_result_index),
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`UNUSED_PIN (valid_out)
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);
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wire [`BR_BITS-1:0] br_op = branch_req_if.br_op;
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wire [31:0] rs1_data = branch_req_if.rs1_data[br_result_index];
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wire [31:0] rs2_data = branch_req_if.rs2_data[br_result_index];
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wire [32:0] sub_in1 = {(br_op != `BR_LTU) & (br_op != `BR_GEU) & rs1_data[31], rs1_data};
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wire [32:0] sub_in2 = {(br_op != `BR_LTU) & (br_op != `BR_GEU) & rs2_data[31], rs2_data};
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wire [32:0] sub_res = $signed(sub_in1) - $signed(sub_in2);
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wire sub_sign = sub_res[32];
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wire sub_nzero = (| sub_res[31:0]);
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reg br_taken;
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always @(*) begin
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case (br_op)
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`BR_NE: br_taken = sub_nzero;
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`BR_EQ: br_taken = ~sub_nzero;
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`BR_LT,
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`BR_LTU: br_taken = sub_sign;
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`BR_GE,
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`BR_GEU: br_taken = ~sub_sign;
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default: br_taken = 1'b1;
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endcase
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end
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wire in_valid = (| branch_req_if.valid);
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wire [31:0] base_addr = (br_op == `BR_JALR) ? rs1_data : branch_req_if.curr_PC;
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wire [31:0] br_dest = $signed(base_addr) + $signed(branch_req_if.offset);
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wire stall = (~branch_commit_if.ready && (| branch_commit_if.valid));
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VX_generic_register #(
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.N(1 + `NW_BITS + 1 + 32)
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) rsp_reg (
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.clk (clk),
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.reset (reset),
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.stall (stall),
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.flush (0),
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.in ({in_valid, branch_req_if.warp_num, br_taken, br_dest}),
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.out ({branch_ctl_if.valid, branch_ctl_if.warp_num, branch_ctl_if.taken, branch_ctl_if.dest})
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);
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VX_generic_register #(
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.N(`NUM_THREADS + `NW_BITS + 32 + `NR_BITS + `WB_BITS + (`NUM_THREADS * 32)),
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) wb_reg (
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.clk (clk),
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.reset (reset),
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.stall (stall),
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.flush (0),
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.in ({branch_req_if.valid, branch_req_if.warp_num, branch_req_if.curr_PC, branch_req_if.rd, branch_req_if.wb, {`NUM_THREADS{branch_req_if.next_PC}}}),
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.out ({branch_commit_if.valid, branch_commit_if.warp_num, branch_commit_if.curr_PC, branch_commit_if.rd, branch_commit_if.wb, branch_commit_if.data})
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);
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assign branch_req_if.ready = ~stall;
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endmodule |