67 lines
2.1 KiB
Verilog
67 lines
2.1 KiB
Verilog
`include "VX_define.vh"
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module VX_gpr_wrapper (
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input wire clk,
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input wire reset,
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VX_gpr_read_if gpr_read_if,
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VX_wb_if writeback_if,
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VX_gpr_jal_if gpr_jal_if,
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output wire[`NUM_THREADS-1:0][31:0] a_reg_data,
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output wire[`NUM_THREADS-1:0][31:0] b_reg_data
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);
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wire[`NUM_WARPS-1:0][`NUM_THREADS-1:0][31:0] temp_a_reg_data;
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wire[`NUM_WARPS-1:0][`NUM_THREADS-1:0][31:0] temp_b_reg_data;
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wire[`NUM_THREADS-1:0][31:0] jal_data;
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genvar i;
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generate
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for (i = 0; i < `NUM_THREADS; i++) begin : jal_data_assign
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assign jal_data[i] = gpr_jal_if.curr_PC;
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end
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endgenerate
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`ifndef ASIC
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assign a_reg_data = (gpr_jal_if.is_jal ? jal_data : (temp_a_reg_data[gpr_read_if.warp_num]));
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assign b_reg_data = (temp_b_reg_data[gpr_read_if.warp_num]);
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`else
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wire zer = 0;
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wire[`NW_BITS-1:0] old_warp_num;
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VX_generic_register #(
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.N(`NW_BITS-1+1)
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) store_wn (
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.clk (clk),
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.reset(reset),
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.stall(zer),
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.flush(zer),
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.in (gpr_read_if.warp_num),
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.out (old_warp_num)
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);
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assign a_reg_data = (gpr_jal_if.is_jal ? jal_data : (temp_a_reg_data[old_warp_num]));
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assign b_reg_data = (temp_b_reg_data[old_warp_num]);
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`endif
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generate
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for (i = 0; i < `NUM_WARPS; i++) begin : warp_gprs
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wire valid_write_request = i == writeback_if.warp_num;
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VX_gpr gpr(
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.clk (clk),
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.reset (reset),
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.valid_write_request (valid_write_request),
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.gpr_read_if (gpr_read_if),
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.writeback_if (writeback_if),
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.a_reg_data (temp_a_reg_data[i]),
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.b_reg_data (temp_b_reg_data[i])
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);
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end
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endgenerate
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endmodule
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