34 lines
688 B
Verilog
34 lines
688 B
Verilog
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`include "VX_define.v"
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module VX_m_w_reg (
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input wire clk,
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input wire reset,
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input wire in_freeze,
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VX_inst_mem_wb_inter VX_mem_wb,
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VX_mw_wb_inter VX_mw_wb
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);
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wire flush = 0;
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wire stall = in_freeze;
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VX_generic_register #(.N(303)) m_w_reg
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(
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.clk (clk),
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.reset(reset),
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.stall(stall),
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.flush(flush),
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.in ({VX_mem_wb.alu_result, VX_mem_wb.mem_result, VX_mem_wb.rd, VX_mem_wb.wb, VX_mem_wb.PC_next, VX_mem_wb.valid, VX_mem_wb.warp_num}),
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.out ({VX_mw_wb.alu_result , VX_mw_wb.mem_result , VX_mw_wb.rd , VX_mw_wb.wb , VX_mw_wb.PC_next , VX_mw_wb.valid , VX_mw_wb.warp_num })
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);
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endmodule // VX_m_w_reg
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