33 lines
407 B
Verilog
33 lines
407 B
Verilog
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`include "VX_define.v"
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`ifndef VX_CSR_W_REQ
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`define VX_CSR_W_REQ
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interface VX_csr_write_request_inter ();
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wire is_csr;
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wire[11:0] csr_address;
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wire[31:0] csr_result;
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// source-side view
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modport snk (
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input is_csr,
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input csr_address,
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input csr_result
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);
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// source-side view
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modport src (
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output is_csr,
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output csr_address,
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output csr_result
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);
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endinterface
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`endif |