8 lines
378 B
Plaintext
8 lines
378 B
Plaintext
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# Analysis & Synthesis Assignments
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set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
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# set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ON
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set_global_assignment -name VERILOG_MACRO QUARTUS
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set_global_assignment -name VERILOG_MACRO SYNTHESIS
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set_global_assignment -name VERILOG_MACRO NDEBUG
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set_global_assignment -name MESSAGE_DISABLE 16818 |