56 lines
2.3 KiB
Verilog
56 lines
2.3 KiB
Verilog
`include "VX_tex_define.vh"
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module VX_tex_format #(
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parameter CORE_ID = 0,
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parameter NUM_TEXELS = 4 //BILINEAR
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) (
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input wire [NUM_TEXELS-1:0][31:0] texel_data,
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input wire [`TEX_FORMAT_BITS-1:0] format,
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output wire [`NUM_COLOR_CHANNEL-1:0] color_enable,
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output wire [NUM_TEXELS-1:0][63:0] formatted_texel
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);
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`UNUSED_PARAM (CORE_ID)
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reg [`NUM_COLOR_CHANNEL-1:0] color_enable_r;
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reg [NUM_TEXELS-1:0][63:0] formatted_texel_r;
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always @(*) begin
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for (integer i = 0; i<NUM_TEXELS ;i++ ) begin
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case (format)
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`TEX_FORMAT_R5G6B5: begin
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formatted_texel_r[i][55:48] = `TEX_COLOR_BITS'(texel_data[i][15:11]);
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formatted_texel_r[i][39:32] = `TEX_COLOR_BITS'(texel_data[i][10:5]);
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formatted_texel_r[i][23:16] = `TEX_COLOR_BITS'(texel_data[i][4:0]);
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formatted_texel_r[i][7:0] = {`TEX_COLOR_BITS{1'b0}};
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if (i == 0)
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color_enable_r = 4'b1110;
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end
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`TEX_FORMAT_R8G8B8: begin
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formatted_texel_r[i][55:48] = `TEX_COLOR_BITS'(texel_data[i][23:16]);
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formatted_texel_r[i][39:32] = `TEX_COLOR_BITS'(texel_data[i][15:8]);
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formatted_texel_r[i][23:16] = `TEX_COLOR_BITS'(texel_data[i][7:0]);
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formatted_texel_r[i][7:0] = {`TEX_COLOR_BITS{1'b0}};
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if (i == 0)
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color_enable_r = 4'b1110;
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end
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default: begin // `TEX_FORMAT_R8G8B8A8:
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formatted_texel_r[i][55:48] = `TEX_COLOR_BITS'(texel_data[i][31:24]);
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formatted_texel_r[i][39:32] = `TEX_COLOR_BITS'(texel_data[i][23:16]);
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formatted_texel_r[i][23:16] = `TEX_COLOR_BITS'(texel_data[i][15:8]);
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formatted_texel_r[i][7:0] = `TEX_COLOR_BITS'(texel_data[i][7:0]);
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if (i == 0)
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color_enable_r = 4'b1111;
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end
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endcase
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end
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end
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assign color_enable = color_enable_r;
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for (genvar i = 0;i<NUM_TEXELS ;i++ ) begin
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assign formatted_texel[i] = formatted_texel_r[i] & 64'h00ff00ff00ff00ff;
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end
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endmodule
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