152 lines
4.2 KiB
Verilog
152 lines
4.2 KiB
Verilog
`include "VX_platform.vh"
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module VX_dp_ram #(
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parameter DATAW = 1,
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parameter SIZE = 1,
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parameter BYTEENW = 1,
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parameter BUFFERED = 1,
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parameter RWCHECK = 1,
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parameter RWBYPASS = 0,
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parameter ADDRW = $clog2(SIZE),
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parameter SIZEW = $clog2(SIZE+1)
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) (
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input wire clk,
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input wire [ADDRW-1:0] waddr,
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input wire [ADDRW-1:0] raddr,
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input wire wren,
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input wire [BYTEENW-1:0] byteen,
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input wire rden,
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input wire [DATAW-1:0] din,
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output wire [DATAW-1:0] dout
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);
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if (BUFFERED) begin
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reg [DATAW-1:0] mem [SIZE-1:0];
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reg [DATAW-1:0] dout_r;
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if (BYTEENW > 1) begin
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always @(posedge clk) begin
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if (wren) begin
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for (integer i = 0; i < BYTEENW; i++) begin
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if (byteen[i])
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mem[waddr][i * 8 +: 8] <= din[i * 8 +: 8];
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end
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end
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end
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end else begin
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always @(posedge clk) begin
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if (wren && byteen)
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mem[waddr] <= din;
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end
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end
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always @(posedge clk) begin
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if (rden)
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dout_r <= mem[raddr];
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end
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if (RWBYPASS) begin
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reg [DATAW-1:0] din_r;
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wire writing;
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if (BYTEENW > 1) begin
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always @(posedge clk) begin
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if (wren) begin
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for (integer i = 0; i < BYTEENW; i++) begin
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din_r[i * 8 +: 8] <= byteen[i] ? din[i * 8 +: 8] : mem[waddr][i * 8 +: 8];
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end
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end
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end
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end else begin
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always @(posedge clk) begin
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din_r <= din;
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end
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end
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reg bypass_r;
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always @(posedge clk) begin
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bypass_r <= wren && (raddr == waddr);
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end
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assign dout = bypass_r ? din_r : dout_r;
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end else begin
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assign dout = dout_r;
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end
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end else begin
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`UNUSED_VAR (rden)
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if (RWCHECK) begin
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reg [DATAW-1:0] mem [SIZE-1:0];
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if (BYTEENW > 1) begin
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always @(posedge clk) begin
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if (wren) begin
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for (integer i = 0; i < BYTEENW; i++) begin
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if (byteen[i])
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mem[waddr][i * 8 +: 8] <= din[i * 8 +: 8];
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end
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end
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end
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end else begin
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always @(posedge clk) begin
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if (wren && byteen)
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mem[waddr] <= din;
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end
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end
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if (RWBYPASS) begin
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reg [DATAW-1:0] din_r;
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wire writing;
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if (BYTEENW > 1) begin
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always @(posedge clk) begin
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if (wren) begin
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for (integer i = 0; i < BYTEENW; i++) begin
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din_r[i * 8 +: 8] <= byteen[i] ? din[i * 8 +: 8] : mem[waddr][i * 8 +: 8];
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end
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end
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end
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end else begin
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always @(posedge clk) begin
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din_r <= din;
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end
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end
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reg bypass_r;
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always @(posedge clk) begin
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bypass_r <= writing && (raddr == waddr);
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end
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assign dout = bypass_r ? din_r : mem[raddr];
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end else begin
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assign dout = mem[raddr];
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end
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end else begin
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`NO_RW_RAM_CHECK reg [DATAW-1:0] mem [SIZE-1:0];
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if (BYTEENW > 1) begin
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always @(posedge clk) begin
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if (wren) begin
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for (integer i = 0; i < BYTEENW; i++) begin
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if (byteen[i])
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mem[waddr][i * 8 +: 8] <= din[i * 8 +: 8];
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end
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end
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end
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end else begin
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always @(posedge clk) begin
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if (wren && byteen)
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mem[waddr] <= din;
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end
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end
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assign dout = mem[raddr];
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end
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end
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endmodule |