d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
77 lines
2.3 KiB
Systemverilog
77 lines
2.3 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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// Fast Paralllel scan using Kogge-Stone style prefix tree with configurable operator
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// Adapted from BaseJump STL: http://bjump.org/index.html
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`TRACING_OFF
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module VX_scan #(
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parameter N = 1,
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parameter OP = 0, // 0: XOR, 1: AND, 2: OR
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parameter REVERSE = 0 // 0: LO->HI, 1: HI->LO
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) (
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input wire [N-1:0] data_in,
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output wire [N-1:0] data_out
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);
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localparam LOGN = `CLOG2(N);
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`IGNORE_UNOPTFLAT_BEGIN
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wire [LOGN:0][N-1:0] t;
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`IGNORE_UNOPTFLAT_END
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// reverses bits
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if (REVERSE != 0) begin
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assign t[0] = data_in;
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end else begin
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assign t[0] = {<<{data_in}};
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end
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// optimize for the common case of small and-scans
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if ((N == 2) && (OP == 1)) begin
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assign t[LOGN] = {t[0][1], &t[0][1:0]};
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end else if ((N == 3) && (OP == 1)) begin
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assign t[LOGN] = {t[0][2], &t[0][2:1], &t[0][2:0]};
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end else if ((N == 4) && (OP == 1)) begin
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assign t[LOGN] = {t[0][3], &t[0][3:2], &t[0][3:1], &t[0][3:0]};
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end else begin
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// general case
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wire [N-1:0] fill;
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for (genvar i = 0; i < LOGN; ++i) begin
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wire [N-1:0] shifted = N'({fill, t[i]} >> (1<<i));
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if (OP == 0) begin
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assign fill = {N{1'b0}};
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assign t[i+1] = t[i] ^ shifted;
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end else if (OP == 1) begin
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assign fill = {N{1'b1}};
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assign t[i+1] = t[i] & shifted;
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end else if (OP == 2) begin
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assign fill = {N{1'b0}};
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assign t[i+1] = t[i] | shifted;
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end
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end
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end
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// reverse bits
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if (REVERSE != 0) begin
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assign data_out = t[LOGN];
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end else begin
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for (genvar i = 0; i < N; ++i) begin
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assign data_out[i] = t[LOGN][N-1-i];
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end
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end
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endmodule
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`TRACING_ON
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