24 lines
581 B
Verilog
24 lines
581 B
Verilog
`ifndef VX_GPU_DCACHE_RES
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`define VX_GPU_DCACHE_RES
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`include "../generic_cache/VX_cache_config.vh"
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interface VX_gpu_dcache_res_inter
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#(
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parameter NUM_REQUESTS = 32
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) ();
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// Cache WB
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wire [NUM_REQUESTS-1:0] core_wb_valid;
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wire [4:0] core_wb_req_rd;
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wire [1:0] core_wb_req_wb;
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wire [`NW_BITS-1:0] core_wb_warp_num;
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wire [NUM_REQUESTS-1:0][31:0] core_wb_readdata;
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wire [NUM_REQUESTS-1:0][31:0] core_wb_pc;
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// Cache Full
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wire delay_req;
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endinterface
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`endif |