+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
141 lines
4.6 KiB
C++
141 lines
4.6 KiB
C++
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include "pipeline.h"
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#include <queue>
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namespace vortex {
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class Dispatcher : public SimObject<Dispatcher> {
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public:
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std::vector<SimPort<pipeline_trace_t*>> Outputs;
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Dispatcher(const SimContext& ctx, const Arch& arch, uint32_t buf_size, uint32_t block_size, uint32_t num_lanes)
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: SimObject<Dispatcher>(ctx, "Dispatcher")
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, Outputs(ISSUE_WIDTH, this)
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, Inputs_(ISSUE_WIDTH, this)
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, arch_(arch)
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, queues_(ISSUE_WIDTH, std::queue<pipeline_trace_t*>())
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, buf_size_(buf_size)
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, block_size_(block_size)
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, num_lanes_(num_lanes)
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, batch_count_(ISSUE_WIDTH / block_size)
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, pid_count_(arch.num_threads() / num_lanes)
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, batch_idx_(0)
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, start_p_(block_size, 0)
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{}
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virtual ~Dispatcher() {}
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virtual void reset() {
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batch_idx_ = 0;
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for (uint32_t b = 0; b < block_size_; ++b) {
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start_p_.at(b) = 0;
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}
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}
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virtual void tick() {
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for (uint32_t i = 0; i < ISSUE_WIDTH; ++i) {
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auto& queue = queues_.at(i);
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if (queue.empty())
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continue;
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auto trace = queue.front();
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Inputs_.at(i).send(trace, 1);
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queue.pop();
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}
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uint32_t block_sent = 0;
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for (uint32_t b = 0; b < block_size_; ++b) {
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uint32_t i = batch_idx_ * block_size_ + b;
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auto& input = Inputs_.at(i);
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if (input.empty()) {
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++block_sent;
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continue;
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}
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auto& output = Outputs.at(i);
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auto trace = input.front();
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if (pid_count_ != 1) {
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auto start_p = start_p_.at(b);
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if (start_p == -1) {
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++block_sent;
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continue;
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}
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int start(-1), end(-1);
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for (uint32_t j = start_p * num_lanes_, n = arch_.num_threads(); j < n; ++j) {
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if (!trace->tmask.test(j))
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continue;
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if (start == -1)
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start = j;
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end = j;
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}
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start /= num_lanes_;
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end /= num_lanes_;
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auto new_trace = new pipeline_trace_t(*trace);
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new_trace->tmask.reset();
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for (int j = start * num_lanes_, n = j + num_lanes_; j < n; ++j) {
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new_trace->tmask[j] = trace->tmask[j];
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}
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new_trace->pid = start;
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new_trace->sop = (start_p == 0);
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if (start == end) {
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new_trace->eop = 1;
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start_p_.at(b) = -1;
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input.pop();
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++block_sent;
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delete trace;
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} else {
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new_trace->eop = 0;
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start_p_.at(b) = start + 1;
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}
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output.send(new_trace, 1);
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DT(3, "pipeline-dispatch: " << *new_trace);
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} else {
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trace->pid = 0;
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input.pop();
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output.send(trace, 1);
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DT(3, "pipeline-dispatch: " << *trace);
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++block_sent;
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}
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}
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if (block_sent == block_size_) {
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batch_idx_ = (batch_idx_ + 1) % batch_count_;
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for (uint32_t b = 0; b < block_size_; ++b) {
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start_p_.at(b) = 0;
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}
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}
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};
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bool push(uint32_t issue_index, pipeline_trace_t* trace) {
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auto& queue = queues_.at(issue_index);
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if (queue.size() >= buf_size_)
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return false;
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queue.push(trace);
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return true;
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}
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private:
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std::vector<SimPort<pipeline_trace_t*>> Inputs_;
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const Arch& arch_;
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std::vector<std::queue<pipeline_trace_t*>> queues_;
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uint32_t buf_size_;
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uint32_t block_size_;
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uint32_t num_lanes_;
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uint32_t batch_count_;
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uint32_t pid_count_;
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uint32_t batch_idx_;
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std::vector<int> start_p_;
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};
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} |