c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
44 lines
1.1 KiB
Systemverilog
44 lines
1.1 KiB
Systemverilog
// Copyright © 2019-2023
|
|
//
|
|
// Licensed under the Apache License, Version 2.0 (the "License");
|
|
// you may not use this file except in compliance with the License.
|
|
// You may obtain a copy of the License at
|
|
// http://www.apache.org/licenses/LICENSE-2.0
|
|
//
|
|
// Unless required by applicable law or agreed to in writing, software
|
|
// distributed under the License is distributed on an "AS IS" BASIS,
|
|
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
// See the License for the specific language governing permissions and
|
|
// limitations under the License.
|
|
|
|
`include "VX_define.vh"
|
|
|
|
interface VX_mem_perf_if import VX_gpu_pkg::*; ();
|
|
|
|
cache_perf_t icache;
|
|
cache_perf_t dcache;
|
|
cache_perf_t l2cache;
|
|
cache_perf_t l3cache;
|
|
cache_perf_t smem;
|
|
mem_perf_t mem;
|
|
|
|
modport master (
|
|
output icache,
|
|
output dcache,
|
|
output l2cache,
|
|
output l3cache,
|
|
output smem,
|
|
output mem
|
|
);
|
|
|
|
modport slave (
|
|
input icache,
|
|
input dcache,
|
|
input l2cache,
|
|
input l3cache,
|
|
input smem,
|
|
input mem
|
|
);
|
|
|
|
endinterface
|