Blaise Tine 9a9f7955f0 basic test timing + scope tracing ccip

2020-10-27 17:04:04 -04:00

..

VX_bank_core_req_arb.v

mutiple fixes: parallel printf, fixed cycle in cache, opencl refactored vecadd and sgemm, regen opencl kernels with hard-float, fixed vortex io bus interface, fixed dpi floats APi to support multicore mode, make vlsim multicore default, make rtlsim multi-core default, removed POCL binaries from repository, updated Makefiles to use external POCL

2020-09-19 14:45:42 -04:00

VX_bank.v

basic test timing + scope tracing ccip

2020-10-27 17:04:04 -04:00

VX_cache_config.vh

scope refactoring

2020-10-03 18:53:21 -04:00

VX_cache_core_req_bank_sel.v

quartus build fixes

2020-08-23 22:04:46 -07:00

VX_cache_core_rsp_merge.v

scope refactoring: adding modules definitions to VCD trace

2020-10-12 23:26:02 -04:00

VX_cache_dram_fill_arb.v

round robin arbiter + auto buffered queue + fixed dcache arbiter

2020-06-20 17:56:04 -04:00

VX_cache_dram_req_arb.v

mutiple fixes: parallel printf, fixed cycle in cache, opencl refactored vecadd and sgemm, regen opencl kernels with hard-float, fixed vortex io bus interface, fixed dpi floats APi to support multicore mode, make vlsim multicore default, make rtlsim multi-core default, removed POCL binaries from repository, updated Makefiles to use external POCL

2020-09-19 14:45:42 -04:00

VX_cache_miss_resrv.v

vlsim fix, verilator fst trace, use ram optimization

2020-10-25 16:40:50 -07:00

VX_cache.v

scope refactoring: adding modules definitions to VCD trace

2020-10-12 23:26:02 -04:00

VX_snp_forwarder.v

scope refactoring

2020-10-03 18:53:21 -04:00

VX_snp_rsp_arb.v

pipeline refactoring - fmax >= 222 mhz

2020-08-14 21:50:14 -07:00

VX_tag_data_access.v

vlsim fix, verilator fst trace, use ram optimization

2020-10-25 16:40:50 -07:00

VX_tag_data_store.v

vlsim fix, verilator fst trace, use ram optimization

2020-10-25 16:40:50 -07:00