166 lines
5.4 KiB
Verilog
166 lines
5.4 KiB
Verilog
`include "VX_tex_define.vh"
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module VX_tex_addr #(
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parameter CORE_ID = 0,
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parameter REQ_INFO_WIDTH = 1
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) (
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input wire clk,
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input wire reset,
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// handshake
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input wire valid_in,
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output wire ready_in,
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// inputs
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input wire [`NW_BITS-1:0] req_wid,
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input wire [`NUM_THREADS-1:0] req_tmask,
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input wire [31:0] req_PC,
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input wire [REQ_INFO_WIDTH-1:0] req_info,
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input wire [`TEX_FORMAT_BITS-1:0] format,
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input wire [`TEX_FILTER_BITS-1:0] filter,
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input wire [`TEX_WRAP_BITS-1:0] wrap_u,
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input wire [`TEX_WRAP_BITS-1:0] wrap_v,
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input wire [`TEX_ADDR_BITS-1:0] base_addr,
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input wire [`NUM_THREADS-1:0][`TEX_MIPOFF_BITS-1:0] mip_offsets,
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input wire [`NUM_THREADS-1:0][`TEX_WIDTH_BITS-1:0] log_widths,
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input wire [`NUM_THREADS-1:0][`TEX_HEIGHT_BITS-1:0] log_heights,
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input wire [`NUM_THREADS-1:0][31:0] coord_u,
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input wire [`NUM_THREADS-1:0][31:0] coord_v,
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// outputs
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output wire rsp_valid,
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output wire [`NW_BITS-1:0] rsp_wid,
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output wire [`NUM_THREADS-1:0] rsp_tmask,
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output wire [31:0] rsp_PC,
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output wire [`TEX_FILTER_BITS-1:0] rsp_filter,
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output wire [`TEX_STRIDE_BITS-1:0] rsp_stride,
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output wire [`NUM_THREADS-1:0][3:0][31:0] rsp_addr,
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output wire [`NUM_THREADS-1:0][`BLEND_FRAC-1:0] rsp_blend_u,
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output wire [`NUM_THREADS-1:0][`BLEND_FRAC-1:0] rsp_blend_v,
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output wire [REQ_INFO_WIDTH-1:0] rsp_info,
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input wire rsp_ready
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);
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`UNUSED_PARAM (CORE_ID)
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wire [`NUM_THREADS-1:0][1:0][`FIXED_FRAC-1:0] clamped_u;
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wire [`NUM_THREADS-1:0][1:0][`FIXED_FRAC-1:0] clamped_v;
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wire [`TEX_STRIDE_BITS-1:0] log_stride;
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// stride
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VX_tex_stride #(
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.CORE_ID (CORE_ID)
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) tex_stride (
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.format (format),
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.log_stride (log_stride)
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);
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// addressing mode
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for (genvar i = 0; i < `NUM_THREADS; ++i) begin
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wire [31:0] fu[1:0];
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wire [31:0] fv[1:0];
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assign fu[0] = coord_u[i] - (filter ? (`FIXED_HALF >> log_widths[i]) : 0);
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assign fu[1] = coord_u[i] + (filter ? (`FIXED_HALF >> log_widths[i]) : 0);
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assign fv[0] = coord_v[i] - (filter ? (`FIXED_HALF >> log_heights[i]) : 0);
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assign fv[1] = coord_v[i] + (filter ? (`FIXED_HALF >> log_heights[i]) : 0);
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VX_tex_wrap #(
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.CORE_ID (CORE_ID)
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) tex_wrap_u0 (
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.wrap_i (wrap_u),
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.coord_i (fu[0]),
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.coord_o (clamped_u[i][0])
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);
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VX_tex_wrap #(
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.CORE_ID (CORE_ID)
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) tex_wrap_u1 (
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.wrap_i (wrap_u),
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.coord_i (fu[1]),
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.coord_o (clamped_u[i][1])
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);
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VX_tex_wrap #(
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.CORE_ID (CORE_ID)
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) tex_wrap_v0 (
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.wrap_i (wrap_v),
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.coord_i (fv[0]),
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.coord_o (clamped_v[i][0])
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);
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VX_tex_wrap #(
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.CORE_ID (CORE_ID)
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) tex_wrap_v1 (
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.wrap_i (wrap_v),
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.coord_i (fv[1]),
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.coord_o (clamped_v[i][1])
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);
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end
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// addresses generation
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wire [`NUM_THREADS-1:0][3:0][31:0] addr;
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for (genvar i = 0; i < `NUM_THREADS; ++i) begin
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wire [`FIXED_FRAC-1:0] x [1:0];
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wire [`FIXED_FRAC-1:0] y [1:0];
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assign x[0] = clamped_u[i][0] >> ((`FIXED_FRAC) - log_widths[i]);
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assign x[1] = clamped_u[i][1] >> ((`FIXED_FRAC) - log_widths[i]);
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assign y[0] = clamped_v[i][0] >> ((`FIXED_FRAC) - log_heights[i]);
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assign y[1] = clamped_v[i][1] >> ((`FIXED_FRAC) - log_heights[i]);
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assign addr[i][0] = base_addr + 32'(mip_offsets[i]) + (32'(x[0]) + (32'(y[0]) << log_widths[i])) << log_stride;
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assign addr[i][1] = base_addr + 32'(mip_offsets[i]) + (32'(x[1]) + (32'(y[0]) << log_widths[i])) << log_stride;
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assign addr[i][2] = base_addr + 32'(mip_offsets[i]) + (32'(x[0]) + (32'(y[1]) << log_widths[i])) << log_stride;
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assign addr[i][3] = base_addr + 32'(mip_offsets[i]) + (32'(x[1]) + (32'(y[1]) << log_widths[i])) << log_stride;
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end
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wire [`NUM_THREADS-1:0][`BLEND_FRAC-1:0] blend_u, blend_v;
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for (genvar i = 0; i < `NUM_THREADS; ++i) begin
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assign blend_u[i] = clamped_u[i][0][`BLEND_FRAC-1:0];
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assign blend_v[i] = clamped_v[i][0][`BLEND_FRAC-1:0];
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end
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wire stall_out = rsp_valid && ~rsp_ready;
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VX_pipe_register #(
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.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + (`NUM_THREADS * 4 * 32) + (2*`NUM_THREADS * `BLEND_FRAC) + REQ_INFO_WIDTH),
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.RESETW (1)
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) pipe_reg (
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.clk (clk),
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.reset (reset),
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.enable (~stall_out),
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.data_in ({valid_in, req_wid, req_tmask, req_PC, filter, log_stride, addr, blend_u, blend_v, req_info}),
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.data_out ({rsp_valid, rsp_wid, rsp_tmask, rsp_PC, rsp_filter, rsp_stride, rsp_addr, rsp_blend_u, rsp_blend_v, rsp_info})
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);
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assign ready_in = ~stall_out;
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`ifdef DBG_PRINT_TEX
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always @(posedge clk) begin
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if (rsp_valid && rsp_ready) begin
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$write("%t: core%0d-tex-addr: wid=%0d, PC=%0h, tmask=%b, filter=%0d, tride=%0d, addr=",
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$time, CORE_ID, rsp_wid, rsp_PC, rsp_tmask, rsp_filter, rsp_stride);
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`PRINT_ARRAY2D(rsp_addr, 4, `NUM_THREADS);
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$write("\n");
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end
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end
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`endif
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endmodule |