50 lines
1.6 KiB
Verilog
50 lines
1.6 KiB
Verilog
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`include "VX_define.v"
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module VX_e_m_reg (
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input wire clk,
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input wire reset,
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input wire in_freeze,
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input wire[11:0] in_csr_address,
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input wire in_is_csr,
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input wire[31:0] in_csr_result,
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input wire in_jal,
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input wire[31:0] in_jal_dest,
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VX_mem_req_inter VX_exe_mem_req,
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VX_mem_req_inter VX_mem_req,
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output wire[11:0] out_csr_address,
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output wire out_is_csr,
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output wire[31:0] out_csr_result,
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output wire out_jal,
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output wire[31:0] out_jal_dest
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);
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wire flush = 0;
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wire stall = in_freeze;
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wire temp_out_jal;
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assign out_jal = temp_out_jal && VX_mem_req.valid[0];
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VX_generic_register #(.N(463)) f_d_reg
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(
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.clk (clk),
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.reset(reset),
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.stall(stall),
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.flush(flush),
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.in ({in_csr_address , in_is_csr , in_csr_result , in_jal , in_jal_dest , VX_exe_mem_req.alu_result, VX_exe_mem_req.mem_read, VX_exe_mem_req.mem_write, VX_exe_mem_req.rd, VX_exe_mem_req.wb, VX_exe_mem_req.rs1, VX_exe_mem_req.rs2, VX_exe_mem_req.rd2, VX_exe_mem_req.PC_next, VX_exe_mem_req.curr_PC, VX_exe_mem_req.branch_offset, VX_exe_mem_req.branch_type, VX_exe_mem_req.valid, VX_exe_mem_req.warp_num}),
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.out ({out_csr_address, out_is_csr, out_csr_result, temp_out_jal, out_jal_dest, VX_mem_req.alu_result , VX_mem_req.mem_read , VX_mem_req.mem_write , VX_mem_req.rd , VX_mem_req.wb , VX_mem_req.rs1 , VX_mem_req.rs2 , VX_mem_req.rd2 , VX_mem_req.PC_next , VX_mem_req.curr_PC , VX_mem_req.branch_offset , VX_mem_req.branch_type , VX_mem_req.valid , VX_mem_req.warp_num})
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);
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endmodule // VX_e_m_reg
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