6 lines
217 B
Plaintext
6 lines
217 B
Plaintext
# load design
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read_verilog -sv -I../../rtl -I../../rtl/interfaces -I../../rtl/cache -I../../rtl/generic_cache -I../../rtl/shared_memory -I../../rtl/pipe_regs -I../../rtl/compat ../../rtl/Vortex.v
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# dump diagram
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show
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