71 lines
1.8 KiB
Verilog
71 lines
1.8 KiB
Verilog
`include "VX_define.v"
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module VX_gpr_wrapper (
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input wire clk,
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input wire reset,
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VX_gpr_read_inter VX_gpr_read,
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VX_wb_inter VX_writeback_inter,
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VX_gpr_jal_inter VX_gpr_jal,
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output wire[`NT_M1:0][31:0] out_a_reg_data,
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output wire[`NT_M1:0][31:0] out_b_reg_data
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);
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wire[`NW-1:0][`NT_M1:0][31:0] temp_a_reg_data;
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wire[`NW-1:0][`NT_M1:0][31:0] temp_b_reg_data;
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wire[`NT_M1:0][31:0] jal_data;
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genvar index;
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for (index = 0; index <= `NT_M1; index = index + 1) begin
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assign jal_data[index] = VX_gpr_jal.curr_PC;
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end
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`ifndef ASIC
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assign out_a_reg_data = (VX_gpr_jal.is_jal ? jal_data : (temp_a_reg_data[VX_gpr_read.warp_num]));
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assign out_b_reg_data = (temp_b_reg_data[VX_gpr_read.warp_num]);
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`else
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wire zer = 0;
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wire[`NW_M1:0] old_warp_num;
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VX_generic_register #(`NW_M1+1) store_wn(
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.clk (clk),
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.reset(reset),
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.stall(zer),
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.flush(zer),
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.in (VX_gpr_read.warp_num),
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.out (old_warp_num)
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);
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assign out_a_reg_data = (VX_gpr_jal.is_jal ? jal_data : (temp_a_reg_data[old_warp_num]));
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assign out_b_reg_data = (temp_b_reg_data[old_warp_num]);
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`endif
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genvar warp_index;
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generate
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for (warp_index = 0; warp_index < `NW; warp_index = warp_index + 1) begin
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wire valid_write_request = warp_index == VX_writeback_inter.wb_warp_num;
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VX_gpr vx_gpr(
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.clk (clk),
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.reset (reset),
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.valid_write_request(valid_write_request),
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.VX_gpr_read (VX_gpr_read),
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.VX_writeback_inter (VX_writeback_inter),
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.out_a_reg_data (temp_a_reg_data[warp_index]),
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.out_b_reg_data (temp_b_reg_data[warp_index])
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);
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end
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endgenerate
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endmodule
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