167 lines
7.1 KiB
Verilog
167 lines
7.1 KiB
Verilog
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`include "VX_define.v"
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module VX_dmem_controller (
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input wire clk,
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input wire reset,
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// MEM-RAM
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VX_dram_req_rsp_inter VX_dram_req_rsp,
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VX_dram_req_rsp_inter VX_dram_req_rsp_icache,
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// MEM-Processor
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VX_icache_request_inter VX_icache_req,
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VX_icache_response_inter VX_icache_rsp,
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VX_dcache_request_inter VX_dcache_req,
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VX_dcache_response_inter VX_dcache_rsp
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);
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wire to_shm = VX_dcache_req.out_cache_driver_in_address[0][31:24] == 8'hFF;
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wire[`NT_M1:0] sm_driver_in_valid = VX_dcache_req.out_cache_driver_in_valid & {`NT{to_shm}};
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wire[`NT_M1:0] cache_driver_in_valid = VX_dcache_req.out_cache_driver_in_valid & {`NT{~to_shm}};
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wire read_or_write = (VX_dcache_req.out_cache_driver_in_mem_write != `NO_MEM_WRITE) && (|cache_driver_in_valid);
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wire[`NT_M1:0][31:0] cache_driver_in_address = VX_dcache_req.out_cache_driver_in_address;
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wire[2:0] cache_driver_in_mem_read = !(|cache_driver_in_valid) ? `NO_MEM_READ : VX_dcache_req.out_cache_driver_in_mem_read;
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wire[2:0] cache_driver_in_mem_write = !(|cache_driver_in_valid) ? `NO_MEM_WRITE : VX_dcache_req.out_cache_driver_in_mem_write;
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wire[`NT_M1:0][31:0] cache_driver_in_data = VX_dcache_req.out_cache_driver_in_data;
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wire[`NT_M1:0][31:0] cache_driver_out_data;
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wire[`NT_M1:0][31:0] sm_driver_out_data;
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wire[`NT_M1:0] cache_driver_out_valid; // Not used for now
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wire sm_delay;
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wire cache_delay;
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// I_Cache Signals
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wire[31:0] icache_instruction_out;
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wire icache_delay;
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wire icache_driver_in_valid = VX_icache_req.out_cache_driver_in_valid;
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wire[31:0] icache_driver_in_address = VX_icache_req.pc_address;
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wire[2:0] icache_driver_in_mem_read = !(|icache_driver_in_valid) ? `NO_MEM_READ : VX_icache_req.out_cache_driver_in_mem_read;
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wire[2:0] icache_driver_in_mem_write = !(|icache_driver_in_valid) ? `NO_MEM_WRITE : VX_icache_req.out_cache_driver_in_mem_write;
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wire[31:0] icache_driver_in_data = VX_icache_req.out_cache_driver_in_data;
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wire read_or_write_ic = (VX_icache_req.out_cache_driver_in_mem_write != `NO_MEM_WRITE) && (|icache_driver_in_valid);
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wire valid_read_cache = !cache_delay && cache_driver_in_valid[0];
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VX_shared_memory #(.NB(7), .BITS_PER_BANK(3)) shared_memory (
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.clk (clk),
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.reset (reset),
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.in_valid (sm_driver_in_valid),
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.in_address(cache_driver_in_address),
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.in_data (cache_driver_in_data),
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.mem_read (cache_driver_in_mem_read),
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.mem_write (cache_driver_in_mem_write),
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.out_valid (cache_driver_out_valid),
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.out_data (sm_driver_out_data),
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.stall (sm_delay)
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);
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VX_d_cache#(
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.CACHE_SIZE (`DCACHE_SIZE),
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.CACHE_WAYS (`DCACHE_WAYS),
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.CACHE_BLOCK (`DCACHE_BLOCK),
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.CACHE_BANKS (`DCACHE_BANKS),
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.LOG_NUM_BANKS (`DCACHE_LOG_NUM_BANKS),
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.NUM_REQ (`DCACHE_NUM_REQ),
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.LOG_NUM_REQ (`DCACHE_LOG_NUM_REQ),
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.NUM_IND (`DCACHE_NUM_IND),
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.CACHE_WAY_INDEX (`DCACHE_WAY_INDEX),
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.NUM_WORDS_PER_BLOCK (`DCACHE_NUM_WORDS_PER_BLOCK),
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.OFFSET_SIZE_START (`DCACHE_OFFSET_ST),
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.OFFSET_SIZE_END (`DCACHE_OFFSET_ED),
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.TAG_SIZE_START (`DCACHE_TAG_SIZE_START),
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.TAG_SIZE_END (`DCACHE_TAG_SIZE_END),
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.IND_SIZE_START (`DCACHE_IND_SIZE_START),
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.IND_SIZE_END (`DCACHE_IND_SIZE_END),
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.ADDR_TAG_START (`DCACHE_ADDR_TAG_START),
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.ADDR_TAG_END (`DCACHE_ADDR_TAG_END),
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.ADDR_OFFSET_START (`DCACHE_ADDR_OFFSET_ST),
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.ADDR_OFFSET_END (`DCACHE_ADDR_OFFSET_ED),
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.ADDR_IND_START (`DCACHE_IND_ST),
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.ADDR_IND_END (`DCACHE_IND_ED),
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.MEM_ADDR_REQ_MASK (`DCACHE_MEM_REQ_ADDR_MASK)
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)
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dcache
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(
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.clk (clk),
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.rst (reset),
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.i_p_valid (cache_driver_in_valid),
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.i_p_addr (cache_driver_in_address),
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.i_p_writedata (cache_driver_in_data),
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.i_p_read_or_write (read_or_write),
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.i_p_mem_read (cache_driver_in_mem_read),
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.i_p_mem_write (cache_driver_in_mem_write),
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.o_p_readdata (cache_driver_out_data),
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.o_p_delay (cache_delay),
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.o_m_evict_addr (VX_dram_req_rsp.o_m_evict_addr),
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.o_m_read_addr (VX_dram_req_rsp.o_m_read_addr),
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.o_m_valid (VX_dram_req_rsp.o_m_valid),
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.o_m_writedata (VX_dram_req_rsp.o_m_writedata),
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.o_m_read_or_write (VX_dram_req_rsp.o_m_read_or_write),
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.i_m_readdata (VX_dram_req_rsp.i_m_readdata),
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.i_m_ready (VX_dram_req_rsp.i_m_ready)
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);
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VX_d_cache#(
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.CACHE_SIZE (`ICACHE_SIZE),
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.CACHE_WAYS (`ICACHE_WAYS),
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.CACHE_BLOCK (`ICACHE_BLOCK),
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.CACHE_BANKS (`ICACHE_BANKS),
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.LOG_NUM_BANKS (`ICACHE_LOG_NUM_BANKS),
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.NUM_REQ (`ICACHE_NUM_REQ),
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.LOG_NUM_REQ (`ICACHE_LOG_NUM_REQ),
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.NUM_IND (`ICACHE_NUM_IND),
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.CACHE_WAY_INDEX (`ICACHE_WAY_INDEX),
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.NUM_WORDS_PER_BLOCK (`ICACHE_NUM_WORDS_PER_BLOCK),
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.OFFSET_SIZE_START (`ICACHE_OFFSET_ST),
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.OFFSET_SIZE_END (`ICACHE_OFFSET_ED),
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.TAG_SIZE_START (`ICACHE_TAG_SIZE_START),
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.TAG_SIZE_END (`ICACHE_TAG_SIZE_END),
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.IND_SIZE_START (`ICACHE_IND_SIZE_START),
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.IND_SIZE_END (`ICACHE_IND_SIZE_END),
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.ADDR_TAG_START (`ICACHE_ADDR_TAG_START),
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.ADDR_TAG_END (`ICACHE_ADDR_TAG_END),
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.ADDR_OFFSET_START (`ICACHE_ADDR_OFFSET_ST),
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.ADDR_OFFSET_END (`ICACHE_ADDR_OFFSET_ED),
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.ADDR_IND_START (`ICACHE_IND_ST),
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.ADDR_IND_END (`ICACHE_IND_ED),
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.MEM_ADDR_REQ_MASK (`ICACHE_MEM_REQ_ADDR_MASK)
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) icache
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(
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.clk (clk),
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.rst (reset),
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.i_p_valid (icache_driver_in_valid),
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.i_p_addr (icache_driver_in_address),
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.i_p_writedata (icache_driver_in_data),
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.i_p_read_or_write (read_or_write_ic),
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.i_p_mem_read (icache_driver_in_mem_read),
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.i_p_mem_write (icache_driver_in_mem_write),
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.o_p_readdata (icache_instruction_out),
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.o_p_delay (icache_delay),
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.o_m_evict_addr (VX_dram_req_rsp_icache.o_m_evict_addr),
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.o_m_read_addr (VX_dram_req_rsp_icache.o_m_read_addr),
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.o_m_valid (VX_dram_req_rsp_icache.o_m_valid),
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.o_m_writedata (VX_dram_req_rsp_icache.o_m_writedata),
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.o_m_read_or_write (VX_dram_req_rsp_icache.o_m_read_or_write),
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.i_m_readdata (VX_dram_req_rsp_icache.i_m_readdata),
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.i_m_ready (VX_dram_req_rsp_icache.i_m_ready)
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);
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assign VX_dcache_rsp.in_cache_driver_out_data = to_shm ? sm_driver_out_data : cache_driver_out_data;
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assign VX_dcache_rsp.delay = sm_delay || cache_delay;
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assign VX_icache_rsp.instruction = icache_instruction_out;
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assign VX_icache_rsp.delay = icache_delay;
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endmodule |