40 lines
1.1 KiB
Verilog
40 lines
1.1 KiB
Verilog
`include "VX_cache_config.v"
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module VX_snp_fwd_arb
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#(
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parameter NUMBER_BANKS = 8
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)
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(
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input wire[NUMBER_BANKS-1:0] per_bank_snp_fwd,
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input wire[NUMBER_BANKS-1:0][31:0] per_bank_snp_fwd_addr,
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output reg[NUMBER_BANKS-1:0] per_bank_snp_fwd_pop,
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output wire snp_fwd,
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output wire[31:0] snp_fwd_addr,
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input wire snp_fwd_delay
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);
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wire[NUMBER_BANKS-1:0] qual_per_bank_snp_fwd = per_bank_snp_fwd & {NUMBER_BANKS{!snp_fwd_delay}};
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wire[`vx_clog2(NUMBER_BANKS)-1:0] fsq_bank;
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wire fsq_valid;
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VX_generic_priority_encoder #(.N(NUMBER_BANKS)) VX_sel_ffsq(
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.valids(qual_per_bank_snp_fwd),
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.index (fsq_bank),
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.found (fsq_valid)
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);
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assign snp_fwd = fsq_valid;
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assign snp_fwd_addr = per_bank_snp_fwd_addr[fsq_bank];
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always @(*) begin
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per_bank_snp_fwd_pop = 0;
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if (fsq_valid) begin
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per_bank_snp_fwd_pop[fsq_bank] = 1;
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end
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end
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endmodule |