62 lines
1.9 KiB
Verilog
62 lines
1.9 KiB
Verilog
`include "VX_cache_config.vh"
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module VX_data_store #(
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// Size of cache in bytes
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parameter CACHE_SIZE = 1,
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// Size of line inside a bank in bytes
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parameter CACHE_LINE_SIZE = 1,
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// Number of banks
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parameter NUM_BANKS = 1,
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// Size of a word in bytes
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parameter WORD_SIZE = 1,
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// Enable cache writeable
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parameter WRITE_ENABLE = 0
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) (
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input wire clk,
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input wire reset,
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input wire write_enable,
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input wire write_fill,
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input wire[CACHE_LINE_SIZE-1:0] byte_enable,
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input wire[`LINE_SELECT_BITS-1:0] write_addr,
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input wire[`CACHE_LINE_WIDTH-1:0] write_data,
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input wire[`LINE_SELECT_BITS-1:0] read_addr,
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output wire[`WORDS_PER_LINE-1:0][WORD_SIZE-1:0] read_dirtyb,
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output wire[`CACHE_LINE_WIDTH-1:0] read_data
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);
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`UNUSED_VAR (reset)
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if (WRITE_ENABLE) begin
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reg [`WORDS_PER_LINE-1:0][WORD_SIZE-1:0] dirtyb[`LINES_PER_BANK-1:0];
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always @(posedge clk) begin
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if (write_enable) begin
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dirtyb[write_addr] <= write_fill ? 0 : (dirtyb[write_addr] | byte_enable);
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end
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end
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assign read_dirtyb = dirtyb [read_addr];
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end else begin
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`UNUSED_VAR (write_fill)
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`UNUSED_VAR (byte_enable)
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assign read_dirtyb = 0;
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end
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VX_dp_ram #(
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.DATAW(CACHE_LINE_SIZE * 8),
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.SIZE(`LINES_PER_BANK),
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.BYTEENW(CACHE_LINE_SIZE),
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.RWCHECK(1)
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) data (
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.clk(clk),
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.waddr(write_addr),
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.raddr(read_addr),
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.wren(write_enable),
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.byteen(byte_enable),
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.rden(1'b1),
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.din(write_data),
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.dout(read_data)
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);
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endmodule
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