10542 lines
492 KiB
Plaintext
10542 lines
492 KiB
Plaintext
$version Generated by VerilatedVcd $end
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$date Mon Jul 13 23:53:11 2020
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$end
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$timescale 1ns $end
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$scope module TOP $end
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$var wire 1 Sh" clk $end
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$var wire 120 {h" core_req_addr [119:0] $end
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$var wire 16 sh" core_req_byteen [15:0] $end
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$var wire 128 =i" core_req_data [127:0] $end
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$var wire 1 mi" core_req_ready $end
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$var wire 4 kh" core_req_rw [3:0] $end
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$var wire 42 ]i" core_req_tag [41:0] $end
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$var wire 4 ch" core_req_valid [3:0] $end
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$var wire 128 }i" core_rsp_data [127:0] $end
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$var wire 1 Oj" core_rsp_ready $end
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$var wire 42 ?j" core_rsp_tag [41:0] $end
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$var wire 4 ui" core_rsp_valid [3:0] $end
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$var wire 28 oj" dram_req_addr [27:0] $end
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$var wire 16 gj" dram_req_byteen [15:0] $end
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$var wire 128 wj" dram_req_data [127:0] $end
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$var wire 1 Ak" dram_req_ready $end
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$var wire 1 _j" dram_req_rw $end
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$var wire 28 9k" dram_req_tag [27:0] $end
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$var wire 1 Wj" dram_req_valid $end
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$var wire 128 Qk" dram_rsp_data [127:0] $end
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$var wire 1 yk" dram_rsp_ready $end
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$var wire 28 qk" dram_rsp_tag [27:0] $end
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$var wire 1 Ik" dram_rsp_valid $end
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$var wire 1 [h" reset $end
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$var wire 2 Em" snp_fwdin_ready [1:0] $end
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$var wire 2 =m" snp_fwdin_tag [1:0] $end
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$var wire 2 5m" snp_fwdin_valid [1:0] $end
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$var wire 56 kl" snp_fwdout_addr [55:0] $end
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$var wire 2 {l" snp_fwdout_invalidate [1:0] $end
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$var wire 2 -m" snp_fwdout_ready [1:0] $end
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$var wire 2 %m" snp_fwdout_tag [1:0] $end
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$var wire 2 cl" snp_fwdout_valid [1:0] $end
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$var wire 28 +l" snp_req_addr [27:0] $end
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$var wire 1 3l" snp_req_invalidate $end
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$var wire 1 Cl" snp_req_ready $end
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$var wire 28 ;l" snp_req_tag [27:0] $end
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$var wire 1 #l" snp_req_valid $end
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$var wire 1 [l" snp_rsp_ready $end
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$var wire 28 Sl" snp_rsp_tag [27:0] $end
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$var wire 1 Kl" snp_rsp_valid $end
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$scope module VX_cache $end
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$var wire 32 gn" BANK_LINE_SIZE [31:0] $end
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$var wire 32 Wn" CACHE_ID [31:0] $end
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$var wire 32 _n" CACHE_SIZE [31:0] $end
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$var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end
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$var wire 32 !o" CORE_TAG_WIDTH [31:0] $end
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$var wire 32 on" CREQ_SIZE [31:0] $end
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$var wire 32 on" CWBQ_SIZE [31:0] $end
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$var wire 32 gn" DFPQ_SIZE [31:0] $end
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$var wire 32 on" DFQQ_SIZE [31:0] $end
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$var wire 32 wn" DRAM_ENABLE [31:0] $end
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$var wire 32 1o" DRAM_TAG_WIDTH [31:0] $end
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$var wire 32 on" DWBQ_SIZE [31:0] $end
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$var wire 32 gn" MRVQ_SIZE [31:0] $end
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$var wire 32 on" NUM_BANKS [31:0] $end
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$var wire 32 on" NUM_REQUESTS [31:0] $end
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$var wire 32 9o" NUM_SNP_REQUESTS [31:0] $end
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$var wire 32 wn" PRFQ_SIZE [31:0] $end
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$var wire 32 Wn" PRFQ_STRIDE [31:0] $end
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$var wire 32 Wn" SNOOP_FORWARDING [31:0] $end
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$var wire 32 wn" SNP_FWD_TAG_WIDTH [31:0] $end
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$var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end
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$var wire 32 gn" SNRQ_SIZE [31:0] $end
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$var wire 32 wn" STAGE_1_CYCLES [31:0] $end
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$var wire 32 on" WORD_SIZE [31:0] $end
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$var wire 32 wn" WRITE_ENABLE [31:0] $end
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$var wire 1 Sh" clk $end
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$var wire 120 {h" core_req_addr [119:0] $end
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$var wire 16 sh" core_req_byteen [15:0] $end
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$var wire 128 =i" core_req_data [127:0] $end
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$var wire 1 mi" core_req_ready $end
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$var wire 4 kh" core_req_rw [3:0] $end
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$var wire 42 ]i" core_req_tag [41:0] $end
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$var wire 4 ch" core_req_valid [3:0] $end
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$var wire 128 }i" core_rsp_data [127:0] $end
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$var wire 1 Oj" core_rsp_ready $end
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$var wire 42 ?j" core_rsp_tag [41:0] $end
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$var wire 4 ui" core_rsp_valid [3:0] $end
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$var wire 1 )-! dram_fill_req_ready $end
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$var wire 28 oj" dram_req_addr [27:0] $end
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$var wire 16 gj" dram_req_byteen [15:0] $end
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$var wire 128 wj" dram_req_data [127:0] $end
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$var wire 1 Ak" dram_req_ready $end
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$var wire 1 _j" dram_req_rw $end
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$var wire 28 9k" dram_req_tag [27:0] $end
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$var wire 1 Wj" dram_req_valid $end
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$var wire 128 Qk" dram_rsp_data [127:0] $end
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$var wire 1 yk" dram_rsp_ready $end
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$var wire 28 qk" dram_rsp_tag [27:0] $end
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$var wire 1 Ik" dram_rsp_valid $end
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$var wire 4 Y+ per_bank_core_req_ready [3:0] $end
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$var wire 128 q+ per_bank_core_rsp_data [127:0] $end
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$var wire 4 + per_bank_core_rsp_ready [3:0] $end
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$var wire 168 3, per_bank_core_rsp_tag [167:0] $end
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$var wire 8 i+ per_bank_core_rsp_tid [7:0] $end
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$var wire 4 a+ per_bank_core_rsp_valid [3:0] $end
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$var wire 112 k, per_bank_dram_fill_req_addr [111:0] $end
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$var wire 4 c, per_bank_dram_fill_req_valid [3:0] $end
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$var wire 4 -- per_bank_dram_fill_rsp_ready [3:0] $end
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$var wire 112 M- per_bank_dram_wb_req_addr [111:0] $end
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$var wire 64 =- per_bank_dram_wb_req_byteen [63:0] $end
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$var wire 512 m- per_bank_dram_wb_req_data [511:0] $end
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$var wire 4 3 per_bank_dram_wb_req_ready [3:0] $end
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$var wire 4 5- per_bank_dram_wb_req_valid [3:0] $end
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$var wire 4 1/ per_bank_snp_req_ready [3:0] $end
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$var wire 4 ; per_bank_snp_rsp_ready [3:0] $end
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$var wire 112 A/ per_bank_snp_rsp_tag [111:0] $end
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$var wire 4 9/ per_bank_snp_rsp_valid [3:0] $end
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$var wire 16 # per_bank_valid [15:0] $end
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$var wire 1 [h" reset $end
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$var wire 2 Em" snp_fwdin_ready [1:0] $end
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$var wire 2 =m" snp_fwdin_tag [1:0] $end
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$var wire 2 5m" snp_fwdin_valid [1:0] $end
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$var wire 56 kl" snp_fwdout_addr [55:0] $end
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$var wire 2 {l" snp_fwdout_invalidate [1:0] $end
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$var wire 2 -m" snp_fwdout_ready [1:0] $end
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$var wire 2 %m" snp_fwdout_tag [1:0] $end
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$var wire 2 cl" snp_fwdout_valid [1:0] $end
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$var wire 28 +l" snp_req_addr [27:0] $end
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$var wire 28 +l" snp_req_addr_qual [27:0] $end
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$var wire 1 3l" snp_req_invalidate $end
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$var wire 1 3l" snp_req_invalidate_qual $end
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$var wire 1 Cl" snp_req_ready $end
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$var wire 1 Mm" snp_req_ready_qual $end
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$var wire 28 ;l" snp_req_tag [27:0] $end
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$var wire 28 ;l" snp_req_tag_qual [27:0] $end
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$var wire 1 #l" snp_req_valid $end
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$var wire 1 #l" snp_req_valid_qual $end
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$var wire 1 [l" snp_rsp_ready $end
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$var wire 28 Sl" snp_rsp_tag [27:0] $end
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$var wire 1 Kl" snp_rsp_valid $end
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$scope module cache_core_req_bank_sel $end
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$var wire 32 gn" BANK_LINE_SIZE [31:0] $end
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$var wire 32 on" NUM_BANKS [31:0] $end
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$var wire 32 on" NUM_REQUESTS [31:0] $end
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$var wire 32 on" WORD_SIZE [31:0] $end
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$var wire 120 {h" core_req_addr [119:0] $end
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$var wire 1 mi" core_req_ready $end
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$var wire 4 ch" core_req_valid [3:0] $end
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$var wire 32 Ao" i [31:0] $end
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$var wire 4 Y+ per_bank_ready [3:0] $end
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$var wire 16 # per_bank_valid [15:0] $end
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$scope module genblk2 $end
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$var wire 4 e! per_bank_ready_sel [3:0] $end
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$upscope $end
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$upscope $end
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$scope module cache_core_rsp_merge $end
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$var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end
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$var wire 32 !o" CORE_TAG_WIDTH [31:0] $end
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$var wire 32 on" NUM_BANKS [31:0] $end
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$var wire 32 on" NUM_REQUESTS [31:0] $end
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$var wire 32 on" WORD_SIZE [31:0] $end
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$var wire 1 Sh" clk $end
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$var wire 128 Y7 core_rsp_data [127:0] $end
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$var wire 1 Oj" core_rsp_ready $end
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$var wire 42 y7 core_rsp_tag [41:0] $end
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$var wire 4 ui" core_rsp_valid [3:0] $end
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$var wire 32 Ao" i [31:0] $end
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$var wire 2 +8 main_bank_index [1:0] $end
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$var wire 128 q+ per_bank_core_rsp_data [127:0] $end
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$var wire 4 38 per_bank_core_rsp_pop_unqual [3:0] $end
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$var wire 4 + per_bank_core_rsp_ready [3:0] $end
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$var wire 168 3, per_bank_core_rsp_tag [167:0] $end
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$var wire 8 i+ per_bank_core_rsp_tid [7:0] $end
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$var wire 4 a+ per_bank_core_rsp_valid [3:0] $end
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$var wire 1 [h" reset $end
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$scope module sel_bank $end
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$var wire 32 on" N [31:0] $end
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$var wire 1 Sh" clk $end
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$var wire 2 +8 grant_index [1:0] $end
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$var wire 4 ;8 grant_onehot [3:0] $end
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$var wire 1 C8 grant_valid $end
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$var wire 4 a+ requests [3:0] $end
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$var wire 1 [h" reset $end
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$scope module genblk2 $end
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$var wire 4 ;8 grant_onehot_r [3:0] $end
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$var wire 4 S8 late_value [3:0] $end
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$var wire 1 [2! refill $end
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$var wire 4 c2! refill_original [3:0] $end
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$var wire 4 a+ refill_value [3:0] $end
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$var wire 4 S2! requests_use [3:0] $end
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$var wire 4 K8 update_value [3:0] $end
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$scope module priority_encoder $end
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$var wire 32 on" N [31:0] $end
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$var wire 4 S2! data_in [3:0] $end
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$var wire 2 +8 data_out [1:0] $end
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$var wire 32 [8 i [31:0] $end
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$var wire 1 C8 valid_out $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$scope module cache_dram_req_arb $end
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$var wire 32 gn" BANK_LINE_SIZE [31:0] $end
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$var wire 32 on" DFQQ_SIZE [31:0] $end
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$var wire 32 on" NUM_BANKS [31:0] $end
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$var wire 32 wn" PRFQ_SIZE [31:0] $end
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$var wire 32 Wn" PRFQ_STRIDE [31:0] $end
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$var wire 32 on" WORD_SIZE [31:0] $end
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$var wire 1 Sh" clk $end
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$var wire 1 c4 dfqq_empty $end
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$var wire 1 {.! dfqq_full $end
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$var wire 1 m! dfqq_pop $end
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$var wire 1 k4 dfqq_push $end
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$var wire 1 S4 dfqq_req $end
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$var wire 28 [4 dfqq_req_addr [27:0] $end
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$var wire 1 )-! dram_fill_req_ready $end
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$var wire 28 oj" dram_req_addr [27:0] $end
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$var wire 16 gj" dram_req_byteen [15:0] $end
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$var wire 128 wj" dram_req_data [127:0] $end
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$var wire 1 Ak" dram_req_ready $end
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$var wire 1 _j" dram_req_rw $end
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$var wire 1 Wj" dram_req_valid $end
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$var wire 2 s4 dwb_bank [1:0] $end
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$var wire 1 K4 dwb_valid $end
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$var wire 112 k, per_bank_dram_fill_req_addr [111:0] $end
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$var wire 4 c, per_bank_dram_fill_req_valid [3:0] $end
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$var wire 112 M- per_bank_dram_wb_req_addr [111:0] $end
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$var wire 64 =- per_bank_dram_wb_req_byteen [63:0] $end
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$var wire 512 m- per_bank_dram_wb_req_data [511:0] $end
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$var wire 4 3 per_bank_dram_wb_req_ready [3:0] $end
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$var wire 4 5- per_bank_dram_wb_req_valid [3:0] $end
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$var wire 28 s.! pref_addr [27:0] $end
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$var wire 1 Io" pref_pop $end
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$var wire 1 Io" pref_valid $end
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$var wire 1 [h" reset $end
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$scope module dram_fill_arb $end
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$var wire 32 gn" BANK_LINE_SIZE [31:0] $end
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$var wire 32 on" DFQQ_SIZE [31:0] $end
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$var wire 32 on" NUM_BANKS [31:0] $end
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$var wire 1 Sh" clk $end
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$var wire 1 c4 dfqq_empty $end
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$var wire 1 {.! dfqq_full $end
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$var wire 1 m! dfqq_pop $end
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$var wire 1 k4 dfqq_push $end
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$var wire 1 S4 dfqq_req $end
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$var wire 28 [4 dfqq_req_addr [27:0] $end
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$var wire 1 u/! o_empty $end
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$var wire 1 /6 out_empty $end
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$var wire 112 =5 out_per_bank_dram_fill_req_addr [111:0] $end
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$var wire 4 55 out_per_bank_dram_fill_req_valid [3:0] $end
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$var wire 112 k, per_bank_dram_fill_req_addr [111:0] $end
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$var wire 4 c, per_bank_dram_fill_req_valid [3:0] $end
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$var wire 1 /* pop_qual $end
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$var wire 1 76 push_qual $end
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$var wire 112 e5 qual_bank_dram_fill_req_addr [111:0] $end
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$var wire 1 G6 qual_has_request $end
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$var wire 2 ?6 qual_request_index [1:0] $end
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$var wire 1 [h" reset $end
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$var wire 4 '6 updated_bank_dram_fill_req_valid [3:0] $end
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$var wire 1 }/! use_empty $end
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$var wire 112 U/! use_per_bank_dram_fill_req_addr [111:0] $end
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$var wire 4 M/! use_per_bank_dram_fill_req_valid [3:0] $end
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$var wire 4 ]5 use_per_bqual_bank_dram_fill_req_valid [3:0] $end
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$scope module dfqq_queue $end
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$var wire 32 wn" BUFFERED_OUTPUT [31:0] $end
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$var wire 32 Qo" DATAW [31:0] $end
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$var wire 32 on" SIZE [31:0] $end
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$var wire 1 Sh" clk $end
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$var wire 116 O6 data_in [115:0] $end
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$var wire 116 o6 data_out [115:0] $end
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$var wire 1 u/! empty $end
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$var wire 1 {.! full $end
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$var wire 1 /* pop $end
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$var wire 1 76 push $end
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$var wire 1 u! reading $end
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$var wire 1 [h" reset $end
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$var wire 3 '0! size [2:0] $end
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$var wire 3 '0! size_r [2:0] $end
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$var wire 1 17 writing $end
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$scope module genblk3 $end
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$var wire 116 /0! data(0) [115:0] $end
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$var wire 116 30! data(1) [115:0] $end
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$var wire 116 70! data(2) [115:0] $end
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$var wire 116 ;0! data(3) [115:0] $end
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$scope module genblk2 $end
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$var wire 1 K2! bypass_r $end
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$var wire 116 q1! curr_r [115:0] $end
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$var wire 1 u/! empty_r $end
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$var wire 1 {.! full_r $end
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$var wire 116 Q1! head_r [115:0] $end
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$var wire 2 C2! rd_ptr_next_r [1:0] $end
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$var wire 2 ;2! rd_ptr_r [1:0] $end
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$var wire 2 32! wr_ptr_r [1:0] $end
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$upscope $end
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$upscope $end
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$upscope $end
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$scope module sel_bank $end
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$var wire 32 on" N [31:0] $end
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$var wire 1 Sh" clk $end
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$var wire 2 ?6 grant_index [1:0] $end
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$var wire 4 97 grant_onehot [3:0] $end
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$var wire 1 G6 grant_valid $end
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$var wire 4 ]5 requests [3:0] $end
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$var wire 1 [h" reset $end
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$scope module genblk2 $end
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$var wire 4 97 grant_onehot_r [3:0] $end
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$scope module priority_encoder $end
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$var wire 32 on" N [31:0] $end
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$var wire 4 ]5 data_in [3:0] $end
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$var wire 2 ?6 data_out [1:0] $end
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$var wire 32 A7 i [31:0] $end
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$var wire 1 G6 valid_out $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$scope module prfqq $end
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$var wire 32 gn" BANK_LINE_SIZE [31:0] $end
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$var wire 32 wn" PRFQ_SIZE [31:0] $end
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$var wire 32 Wn" PRFQ_STRIDE [31:0] $end
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$var wire 32 on" WORD_SIZE [31:0] $end
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$var wire 1 Sh" clk $end
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$var wire 28 5/! current_addr [27:0] $end
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$var wire 1 =/! current_empty $end
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$var wire 1 -/! current_full $end
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$var wire 1 -/! current_valid $end
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$var wire 1 Gn" dram_req $end
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$var wire 28 oj" dram_req_addr [27:0] $end
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$var wire 28 s.! pref_addr [27:0] $end
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$var wire 1 Io" pref_pop $end
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$var wire 1 Io" pref_valid $end
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$var wire 1 [h" reset $end
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$var wire 1 {4 update_use $end
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$var wire 28 s.! use_addr [27:0] $end
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$var wire 2 %/! use_valid [1:0] $end
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$scope module pfq_queue $end
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$var wire 32 wn" BUFFERED_OUTPUT [31:0] $end
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$var wire 32 1o" DATAW [31:0] $end
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$var wire 32 wn" SIZE [31:0] $end
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$var wire 1 Sh" clk $end
|
|
$var wire 28 oj" data_in [27:0] $end
|
|
$var wire 28 5/! data_out [27:0] $end
|
|
$var wire 1 =/! empty $end
|
|
$var wire 1 -/! full $end
|
|
$var wire 1 {4 pop $end
|
|
$var wire 1 On" push $end
|
|
$var wire 1 %5 reading $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 1 E/! size [0:0] $end
|
|
$var wire 1 E/! size_r [0:0] $end
|
|
$var wire 1 -5 writing $end
|
|
$scope module genblk2 $end
|
|
$var wire 28 5/! head_r [27:0] $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope module sel_dwb $end
|
|
$var wire 32 on" N [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 2 s4 grant_index [1:0] $end
|
|
$var wire 4 I7 grant_onehot [3:0] $end
|
|
$var wire 1 K4 grant_valid $end
|
|
$var wire 4 5- requests [3:0] $end
|
|
$var wire 1 [h" reset $end
|
|
$scope module genblk2 $end
|
|
$var wire 4 I7 grant_onehot_r [3:0] $end
|
|
$scope module priority_encoder $end
|
|
$var wire 32 on" N [31:0] $end
|
|
$var wire 4 5- data_in [3:0] $end
|
|
$var wire 2 s4 data_out [1:0] $end
|
|
$var wire 32 Q7 i [31:0] $end
|
|
$var wire 1 K4 valid_out $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope module genblk5(0) $end
|
|
$var wire 120 {h" curr_bank_core_req_addr [119:0] $end
|
|
$var wire 16 sh" curr_bank_core_req_byteen [15:0] $end
|
|
$var wire 128 =i" curr_bank_core_req_data [127:0] $end
|
|
$var wire 1 Q-! curr_bank_core_req_ready $end
|
|
$var wire 4 kh" curr_bank_core_req_rw [3:0] $end
|
|
$var wire 42 ]i" curr_bank_core_req_tag [41:0] $end
|
|
$var wire 4 C curr_bank_core_req_valid [3:0] $end
|
|
$var wire 32 i/ curr_bank_core_rsp_data [31:0] $end
|
|
$var wire 1 K curr_bank_core_rsp_ready $end
|
|
$var wire 42 q/ curr_bank_core_rsp_tag [41:0] $end
|
|
$var wire 2 a/ curr_bank_core_rsp_tid [1:0] $end
|
|
$var wire 1 1-! curr_bank_core_rsp_valid $end
|
|
$var wire 26 A-! curr_bank_dram_fill_req_addr [25:0] $end
|
|
$var wire 1 )-! curr_bank_dram_fill_req_ready $end
|
|
$var wire 1 #0 curr_bank_dram_fill_req_valid $end
|
|
$var wire 26 ]m" curr_bank_dram_fill_rsp_addr [25:0] $end
|
|
$var wire 128 Qk" curr_bank_dram_fill_rsp_data [127:0] $end
|
|
$var wire 1 9-! curr_bank_dram_fill_rsp_ready $end
|
|
$var wire 1 Um" curr_bank_dram_fill_rsp_valid $end
|
|
$var wire 26 ;0 curr_bank_dram_wb_req_addr [25:0] $end
|
|
$var wire 16 30 curr_bank_dram_wb_req_byteen [15:0] $end
|
|
$var wire 128 C0 curr_bank_dram_wb_req_data [127:0] $end
|
|
$var wire 1 S curr_bank_dram_wb_req_ready $end
|
|
$var wire 1 +0 curr_bank_dram_wb_req_valid $end
|
|
$var wire 26 mm" curr_bank_snp_req_addr [25:0] $end
|
|
$var wire 1 3l" curr_bank_snp_req_invalidate $end
|
|
$var wire 1 I-! curr_bank_snp_req_ready $end
|
|
$var wire 28 ;l" curr_bank_snp_req_tag [27:0] $end
|
|
$var wire 1 em" curr_bank_snp_req_valid $end
|
|
$var wire 1 [ curr_bank_snp_rsp_ready $end
|
|
$var wire 28 k0 curr_bank_snp_rsp_tag [27:0] $end
|
|
$var wire 1 c0 curr_bank_snp_rsp_valid $end
|
|
$scope module bank $end
|
|
$var wire 32 Yo" BANK_ID [31:0] $end
|
|
$var wire 32 gn" BANK_LINE_SIZE [31:0] $end
|
|
$var wire 32 Wn" CACHE_ID [31:0] $end
|
|
$var wire 32 _n" CACHE_SIZE [31:0] $end
|
|
$var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end
|
|
$var wire 32 !o" CORE_TAG_WIDTH [31:0] $end
|
|
$var wire 32 on" CREQ_SIZE [31:0] $end
|
|
$var wire 32 on" CWBQ_SIZE [31:0] $end
|
|
$var wire 32 gn" DFPQ_SIZE [31:0] $end
|
|
$var wire 32 on" DFQQ_SIZE [31:0] $end
|
|
$var wire 32 wn" DRAM_ENABLE [31:0] $end
|
|
$var wire 32 on" DWBQ_SIZE [31:0] $end
|
|
$var wire 32 gn" MRVQ_SIZE [31:0] $end
|
|
$var wire 32 on" NUM_BANKS [31:0] $end
|
|
$var wire 32 on" NUM_REQUESTS [31:0] $end
|
|
$var wire 32 Wn" SNOOP_FORWARDING [31:0] $end
|
|
$var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end
|
|
$var wire 32 gn" SNRQ_SIZE [31:0] $end
|
|
$var wire 32 wn" STAGE_1_CYCLES [31:0] $end
|
|
$var wire 32 on" WORD_SIZE [31:0] $end
|
|
$var wire 32 wn" WRITE_ENABLE [31:0] $end
|
|
$var wire 26 == addr_st1(0) [25:0] $end
|
|
$var wire 26 ;@ addr_st1e [25:0] $end
|
|
$var wire 26 A-! addr_st2 [25:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 120 {h" core_req_addr [119:0] $end
|
|
$var wire 16 sh" core_req_byteen [15:0] $end
|
|
$var wire 128 =i" core_req_data [127:0] $end
|
|
$var wire 1 Q-! core_req_ready $end
|
|
$var wire 4 kh" core_req_rw [3:0] $end
|
|
$var wire 42 ]i" core_req_tag [41:0] $end
|
|
$var wire 4 C core_req_valid [3:0] $end
|
|
$var wire 32 i/ core_rsp_data [31:0] $end
|
|
$var wire 1 K core_rsp_ready $end
|
|
$var wire 42 q/ core_rsp_tag [41:0] $end
|
|
$var wire 2 a/ core_rsp_tid [1:0] $end
|
|
$var wire 1 1-! core_rsp_valid $end
|
|
$var wire 32 )5! cwbq_data [31:0] $end
|
|
$var wire 1 [6! cwbq_empty $end
|
|
$var wire 1 c6! cwbq_full $end
|
|
$var wire 1 ?* cwbq_pop $end
|
|
$var wire 1 {@ cwbq_push $end
|
|
$var wire 1 9; cwbq_push_stall $end
|
|
$var wire 1 %A cwbq_push_unqual $end
|
|
$var wire 42 G4! cwbq_tag [41:0] $end
|
|
$var wire 2 ?4! cwbq_tid [1:0] $end
|
|
$var wire 26 M9 dfpq_addr_st0 [25:0] $end
|
|
$var wire 1 {2! dfpq_empty $end
|
|
$var wire 128 U9 dfpq_filldata_st0 [127:0] $end
|
|
$var wire 1 %3! dfpq_full $end
|
|
$var wire 1 E9 dfpq_pop $end
|
|
$var wire 1 q; dfpq_pop_unqual $end
|
|
$var wire 1 w> dirty_st1e $end
|
|
$var wire 1 Y5! dirty_st2 $end
|
|
$var wire 16 !? dirtyb_st1e [15:0] $end
|
|
$var wire 16 a5! dirtyb_st2 [15:0] $end
|
|
$var wire 26 A-! dram_fill_req_addr [25:0] $end
|
|
$var wire 1 c@ dram_fill_req_fast $end
|
|
$var wire 1 )-! dram_fill_req_ready $end
|
|
$var wire 1 I; dram_fill_req_stall $end
|
|
$var wire 1 -A dram_fill_req_unqual $end
|
|
$var wire 1 #0 dram_fill_req_valid $end
|
|
$var wire 26 ]m" dram_fill_rsp_addr [25:0] $end
|
|
$var wire 128 Qk" dram_fill_rsp_data [127:0] $end
|
|
$var wire 1 9-! dram_fill_rsp_ready $end
|
|
$var wire 1 Um" dram_fill_rsp_valid $end
|
|
$var wire 26 ;0 dram_wb_req_addr [25:0] $end
|
|
$var wire 16 30 dram_wb_req_byteen [15:0] $end
|
|
$var wire 128 C0 dram_wb_req_data [127:0] $end
|
|
$var wire 1 }! dram_wb_req_fire $end
|
|
$var wire 1 S dram_wb_req_ready $end
|
|
$var wire 1 +0 dram_wb_req_valid $end
|
|
$var wire 1 -7! dwbq_dual_valid_sel $end
|
|
$var wire 1 k6! dwbq_empty $end
|
|
$var wire 1 s6! dwbq_full $end
|
|
$var wire 1 =A dwbq_is_dwb_in $end
|
|
$var wire 1 MA dwbq_is_dwb_out $end
|
|
$var wire 1 EA dwbq_is_snp_in $end
|
|
$var wire 1 UA dwbq_is_snp_out $end
|
|
$var wire 1 G* dwbq_pop $end
|
|
$var wire 1 5A dwbq_push $end
|
|
$var wire 1 A; dwbq_push_stall $end
|
|
$var wire 1 ]A dwbq_push_unqual $end
|
|
$var wire 26 {6! dwbq_req_addr [25:0] $end
|
|
$var wire 1 Q? fill_saw_dirty_st1e $end
|
|
$var wire 1 #6! fill_saw_dirty_st2 $end
|
|
$var wire 1 !; force_request_miss_st1e $end
|
|
$var wire 1 i; going_to_write_st1(0) $end
|
|
$var wire 49 U= inst_meta_st1(0) [48:0] $end
|
|
$var wire 49 i5! inst_meta_st2 [48:0] $end
|
|
$var wire 1 Y; is_fill_in_pipe $end
|
|
$var wire 1 a; is_fill_st1(0) $end
|
|
$var wire 1 g4! is_fill_st2 $end
|
|
$var wire 1 7> is_mrvq_st1(0) $end
|
|
$var wire 1 +@ is_mrvq_st1e $end
|
|
$var wire 1 +@ is_mrvq_st1e_st2 $end
|
|
$var wire 1 C6! is_mrvq_st2 $end
|
|
$var wire 1 '> is_snp_st1(0) $end
|
|
$var wire 1 Y? is_snp_st1e $end
|
|
$var wire 1 +6! is_snp_st2 $end
|
|
$var wire 32 ao" j [31:0] $end
|
|
$var wire 4 I? mem_byteen_st1e [3:0] $end
|
|
$var wire 1 A? mem_rw_st1e $end
|
|
$var wire 1 k@ miss_add $end
|
|
$var wire 26 A-! miss_add_addr [25:0] $end
|
|
$var wire 1 y? miss_add_because_miss $end
|
|
$var wire 1 ;6! miss_add_because_pending $end
|
|
$var wire 4 _4! miss_add_byteen [3:0] $end
|
|
$var wire 32 !5! miss_add_data [31:0] $end
|
|
$var wire 1 s@ miss_add_is_mrvq $end
|
|
$var wire 1 +6! miss_add_is_snp $end
|
|
$var wire 1 W4! miss_add_rw $end
|
|
$var wire 1 36! miss_add_snp_invalidate $end
|
|
$var wire 42 G4! miss_add_tag [41:0] $end
|
|
$var wire 2 ?4! miss_add_tid [1:0] $end
|
|
$var wire 1 c@ miss_add_unqual $end
|
|
$var wire 2 w4! miss_add_wsel [1:0] $end
|
|
$var wire 1 o> miss_st1e $end
|
|
$var wire 1 Q5! miss_st2 $end
|
|
$var wire 26 ]3! mrvq_addr_st0 [25:0] $end
|
|
$var wire 4 '4! mrvq_byteen_st0 [3:0] $end
|
|
$var wire 1 E3! mrvq_full $end
|
|
$var wire 1 S@ mrvq_init_ready_state_hazard_st0_st1 $end
|
|
$var wire 1 [@ mrvq_init_ready_state_hazard_st1e_st1 $end
|
|
$var wire 1 q? mrvq_init_ready_state_st1e $end
|
|
$var wire 1 K@ mrvq_init_ready_state_st2 $end
|
|
$var wire 1 S6! mrvq_init_ready_state_unqual_st2 $end
|
|
$var wire 1 /4! mrvq_is_snp_st0 $end
|
|
$var wire 1 o: mrvq_pending_hazard_st1e $end
|
|
$var wire 1 W: mrvq_pop $end
|
|
$var wire 1 _: mrvq_pop_unqual $end
|
|
$var wire 1 1; mrvq_push_stall $end
|
|
$var wire 1 3@ mrvq_recover_ready_state_st1e $end
|
|
$var wire 1 K6! mrvq_recover_ready_state_st2 $end
|
|
$var wire 1 g: mrvq_rw_st0 $end
|
|
$var wire 1 74! mrvq_snp_invalidate_st0 $end
|
|
$var wire 1 M3! mrvq_stop $end
|
|
$var wire 42 u3! mrvq_tag_st0 [41:0] $end
|
|
$var wire 2 U3! mrvq_tid_st0 [1:0] $end
|
|
$var wire 1 _: mrvq_valid_st0 $end
|
|
$var wire 32 m3! mrvq_writeword_st0 [31:0] $end
|
|
$var wire 2 e3! mrvq_wsel_st0 [1:0] $end
|
|
$var wire 26 3< qual_addr_st0 [25:0] $end
|
|
$var wire 1 {< qual_going_to_write_st0 $end
|
|
$var wire 49 k< qual_inst_meta_st0 [48:0] $end
|
|
$var wire 1 q; qual_is_fill_st0 $end
|
|
$var wire 1 _: qual_is_mrvq_st0 $end
|
|
$var wire 1 %= qual_is_snp_st0 $end
|
|
$var wire 1 -= qual_snp_invalidate_st0 $end
|
|
$var wire 1 +< qual_valid_st0 $end
|
|
$var wire 1 C@ qual_valid_st1e_2 $end
|
|
$var wire 128 K< qual_writedata_st0 [127:0] $end
|
|
$var wire 32 C< qual_writeword_st0 [31:0] $end
|
|
$var wire 2 ;< qual_wsel_st0 [1:0] $end
|
|
$var wire 128 G> readdata_st1e [127:0] $end
|
|
$var wire 128 15! readdata_st2 [127:0] $end
|
|
$var wire 20 g> readtag_st1e [19:0] $end
|
|
$var wire 20 y5! readtag_st2 [19:0] $end
|
|
$var wire 32 ?> readword_st1e [31:0] $end
|
|
$var wire 32 )5! readword_st2 [31:0] $end
|
|
$var wire 1 ); recover_mrvq_state_st2 $end
|
|
$var wire 1 }9 reqq_empty $end
|
|
$var wire 1 -3! reqq_full $end
|
|
$var wire 1 u9 reqq_pop $end
|
|
$var wire 1 y; reqq_pop_unqual $end
|
|
$var wire 1 7* reqq_push $end
|
|
$var wire 30 G: reqq_req_addr_st0 [29:0] $end
|
|
$var wire 4 ?: reqq_req_byteen_st0 [3:0] $end
|
|
$var wire 1 7: reqq_req_rw_st0 $end
|
|
$var wire 1 ': reqq_req_st0 $end
|
|
$var wire 42 53! reqq_req_tag_st0 [41:0] $end
|
|
$var wire 2 /: reqq_req_tid_st0 [1:0] $end
|
|
$var wire 32 O: reqq_req_writeword_st0 [31:0] $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 1 /> snp_invalidate_st1(0) $end
|
|
$var wire 1 a? snp_invalidate_st1e $end
|
|
$var wire 1 36! snp_invalidate_st2 $end
|
|
$var wire 26 mm" snp_req_addr [25:0] $end
|
|
$var wire 1 3l" snp_req_invalidate $end
|
|
$var wire 1 I-! snp_req_ready $end
|
|
$var wire 28 ;l" snp_req_tag [27:0] $end
|
|
$var wire 1 em" snp_req_valid $end
|
|
$var wire 1 '" snp_rsp_fire $end
|
|
$var wire 1 [ snp_rsp_ready $end
|
|
$var wire 28 k0 snp_rsp_tag [27:0] $end
|
|
$var wire 1 c0 snp_rsp_valid $end
|
|
$var wire 1 i? snp_to_mrvq_st1e $end
|
|
$var wire 1 ;6! snp_to_mrvq_st2 $end
|
|
$var wire 26 -9 snrq_addr_st0 [25:0] $end
|
|
$var wire 1 k2! snrq_empty $end
|
|
$var wire 1 s2! snrq_full $end
|
|
$var wire 1 59 snrq_invalidate_st0 $end
|
|
$var wire 1 %9 snrq_pop $end
|
|
$var wire 1 #< snrq_pop_unqual $end
|
|
$var wire 28 =9 snrq_tag_st0 [27:0] $end
|
|
$var wire 28 %7! snrq_tag_st2 [27:0] $end
|
|
$var wire 1 w: st2_pending_hazard_st1e $end
|
|
$var wire 1 Q; stall_bank_pipe $end
|
|
$var wire 42 )? tag_st1e [41:0] $end
|
|
$var wire 2 9? tid_st1e [1:0] $end
|
|
$var wire 1 5= valid_st1(0) $end
|
|
$var wire 1 #@ valid_st1e $end
|
|
$var wire 1 o4! valid_st2 $end
|
|
$var wire 128 e= writedata_st1(0) [127:0] $end
|
|
$var wire 32 M= writeword_st1(0) [31:0] $end
|
|
$var wire 32 !5! writeword_st2 [31:0] $end
|
|
$var wire 2 E= wsel_st1(0) [1:0] $end
|
|
$var wire 2 w4! wsel_st2 [1:0] $end
|
|
$scope module cache_miss_resrv $end
|
|
$var wire 32 Yo" BANK_ID [31:0] $end
|
|
$var wire 32 gn" BANK_LINE_SIZE [31:0] $end
|
|
$var wire 32 Wn" CACHE_ID [31:0] $end
|
|
$var wire 32 !o" CORE_TAG_WIDTH [31:0] $end
|
|
$var wire 32 gn" MRVQ_SIZE [31:0] $end
|
|
$var wire 32 on" NUM_BANKS [31:0] $end
|
|
$var wire 32 on" NUM_REQUESTS [31:0] $end
|
|
$var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end
|
|
$var wire 32 on" WORD_SIZE [31:0] $end
|
|
$var wire 416 'P! addr_table [415:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 4 AQ! dequeue_index [3:0] $end
|
|
$var wire 1 _: dequeue_possible $end
|
|
$var wire 4 QQ! enqueue_index [3:0] $end
|
|
$var wire 1 aQ! enqueue_possible $end
|
|
$var wire 26 ;@ fill_addr_st1 [25:0] $end
|
|
$var wire 4 IQ! head_ptr [3:0] $end
|
|
$var wire 1 IK increment_head $end
|
|
$var wire 1 eE is_fill_st1 $end
|
|
$var wire 1 s@ is_mrvq $end
|
|
$var wire 16 wJ make_ready [15:0] $end
|
|
$var wire 16 !K make_ready_push [15:0] $end
|
|
$var wire 85 }K! metadata_table(0) [84:0] $end
|
|
$var wire 85 "L! metadata_table(1) [84:0] $end
|
|
$var wire 85 =L! metadata_table(10) [84:0] $end
|
|
$var wire 85 @L! metadata_table(11) [84:0] $end
|
|
$var wire 85 CL! metadata_table(12) [84:0] $end
|
|
$var wire 85 FL! metadata_table(13) [84:0] $end
|
|
$var wire 85 IL! metadata_table(14) [84:0] $end
|
|
$var wire 85 LL! metadata_table(15) [84:0] $end
|
|
$var wire 85 %L! metadata_table(2) [84:0] $end
|
|
$var wire 85 (L! metadata_table(3) [84:0] $end
|
|
$var wire 85 +L! metadata_table(4) [84:0] $end
|
|
$var wire 85 .L! metadata_table(5) [84:0] $end
|
|
$var wire 85 1L! metadata_table(6) [84:0] $end
|
|
$var wire 85 4L! metadata_table(7) [84:0] $end
|
|
$var wire 85 7L! metadata_table(8) [84:0] $end
|
|
$var wire 85 :L! metadata_table(9) [84:0] $end
|
|
$var wire 1 k@ miss_add $end
|
|
$var wire 26 A-! miss_add_addr [25:0] $end
|
|
$var wire 4 _4! miss_add_byteen [3:0] $end
|
|
$var wire 32 !5! miss_add_data [31:0] $end
|
|
$var wire 1 +6! miss_add_is_snp $end
|
|
$var wire 1 W4! miss_add_rw $end
|
|
$var wire 1 36! miss_add_snp_invalidate $end
|
|
$var wire 42 G4! miss_add_tag [41:0] $end
|
|
$var wire 2 ?4! miss_add_tid [1:0] $end
|
|
$var wire 2 w4! miss_add_wsel [1:0] $end
|
|
$var wire 26 ]3! miss_resrv_addr_st0 [25:0] $end
|
|
$var wire 4 '4! miss_resrv_byteen_st0 [3:0] $end
|
|
$var wire 32 m3! miss_resrv_data_st0 [31:0] $end
|
|
$var wire 1 E3! miss_resrv_full $end
|
|
$var wire 1 /4! miss_resrv_is_snp_st0 $end
|
|
$var wire 1 W: miss_resrv_pop $end
|
|
$var wire 1 g: miss_resrv_rw_st0 $end
|
|
$var wire 1 74! miss_resrv_snp_invalidate_st0 $end
|
|
$var wire 1 M3! miss_resrv_stop $end
|
|
$var wire 42 u3! miss_resrv_tag_st0 [41:0] $end
|
|
$var wire 2 U3! miss_resrv_tid_st0 [1:0] $end
|
|
$var wire 1 _: miss_resrv_valid_st0 $end
|
|
$var wire 2 e3! miss_resrv_wsel_st0 [1:0] $end
|
|
$var wire 1 K@ mrvq_init_ready_state $end
|
|
$var wire 1 9K mrvq_pop $end
|
|
$var wire 1 1K mrvq_push $end
|
|
$var wire 1 o: pending_hazard $end
|
|
$var wire 1 YK qual_mrvq_init $end
|
|
$var wire 16 9Q! ready_table [15:0] $end
|
|
$var wire 1 AK recover_state $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 4 AQ! schedule_ptr [3:0] $end
|
|
$var wire 5 YQ! size [4:0] $end
|
|
$var wire 4 QQ! tail_ptr [3:0] $end
|
|
$var wire 1 QK update_ready $end
|
|
$var wire 16 )K valid_address_match [15:0] $end
|
|
$var wire 16 1Q! valid_table [15:0] $end
|
|
$upscope $end
|
|
$scope module core_req_arb $end
|
|
$var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end
|
|
$var wire 32 !o" CORE_TAG_WIDTH [31:0] $end
|
|
$var wire 32 on" CREQ_SIZE [31:0] $end
|
|
$var wire 32 on" NUM_REQUESTS [31:0] $end
|
|
$var wire 32 on" WORD_SIZE [31:0] $end
|
|
$var wire 120 {h" bank_addr [119:0] $end
|
|
$var wire 16 sh" bank_byteen [15:0] $end
|
|
$var wire 4 kh" bank_rw [3:0] $end
|
|
$var wire 42 ]i" bank_tag [41:0] $end
|
|
$var wire 4 C bank_valids [3:0] $end
|
|
$var wire 128 =i" bank_writedata [127:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 1 eC! o_empty $end
|
|
$var wire 1 YC out_empty $end
|
|
$var wire 120 gB out_per_addr [119:0] $end
|
|
$var wire 16 _B out_per_byteen [15:0] $end
|
|
$var wire 4 WB out_per_rw [3:0] $end
|
|
$var wire 42 IC out_per_tag [41:0] $end
|
|
$var wire 4 OB out_per_valids [3:0] $end
|
|
$var wire 128 )C out_per_writedata [127:0] $end
|
|
$var wire 1 aC pop_qual $end
|
|
$var wire 1 O* push_qual $end
|
|
$var wire 120 %C! qual_addr [119:0] $end
|
|
$var wire 16 {B! qual_byteen [15:0] $end
|
|
$var wire 1 ': qual_has_request $end
|
|
$var wire 2 /: qual_request_index [1:0] $end
|
|
$var wire 4 sB! qual_rw [3:0] $end
|
|
$var wire 42 53! qual_tag [41:0] $end
|
|
$var wire 4 kB! qual_valids [3:0] $end
|
|
$var wire 128 EC! qual_writedata [127:0] $end
|
|
$var wire 4 iC real_out_per_valids [3:0] $end
|
|
$var wire 1 }9 reqq_empty $end
|
|
$var wire 1 -3! reqq_full $end
|
|
$var wire 1 u9 reqq_pop $end
|
|
$var wire 1 7* reqq_push $end
|
|
$var wire 30 G: reqq_req_addr_st0 [29:0] $end
|
|
$var wire 4 ?: reqq_req_byteen_st0 [3:0] $end
|
|
$var wire 1 7: reqq_req_rw_st0 $end
|
|
$var wire 1 ': reqq_req_st0 $end
|
|
$var wire 42 53! reqq_req_tag_st0 [41:0] $end
|
|
$var wire 2 /: reqq_req_tid_st0 [1:0] $end
|
|
$var wire 32 O: reqq_req_writedata_st0 [31:0] $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 1 mC! use_empty $end
|
|
$var wire 120 %C! use_per_addr [119:0] $end
|
|
$var wire 16 {B! use_per_byteen [15:0] $end
|
|
$var wire 4 sB! use_per_rw [3:0] $end
|
|
$var wire 42 53! use_per_tag [41:0] $end
|
|
$var wire 4 kB! use_per_valids [3:0] $end
|
|
$var wire 128 EC! use_per_writedata [127:0] $end
|
|
$scope module reqq_queue $end
|
|
$var wire 32 wn" BUFFERED_OUTPUT [31:0] $end
|
|
$var wire 32 yo" DATAW [31:0] $end
|
|
$var wire 32 on" SIZE [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 314 w" data_in [313:0] $end
|
|
$var wire 314 qC data_out [313:0] $end
|
|
$var wire 1 eC! empty $end
|
|
$var wire 1 -3! full $end
|
|
$var wire 1 aC pop $end
|
|
$var wire 1 O* push $end
|
|
$var wire 1 cD reading $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 3 uC! size [2:0] $end
|
|
$var wire 3 uC! size_r [2:0] $end
|
|
$var wire 1 i# writing $end
|
|
$scope module genblk3 $end
|
|
$var wire 314 }C! data(0) [313:0] $end
|
|
$var wire 314 )D! data(1) [313:0] $end
|
|
$var wire 314 3D! data(2) [313:0] $end
|
|
$var wire 314 =D! data(3) [313:0] $end
|
|
$scope module genblk2 $end
|
|
$var wire 1 AI! bypass_r $end
|
|
$var wire 314 7H! curr_r [313:0] $end
|
|
$var wire 1 eC! empty_r $end
|
|
$var wire 1 -3! full_r $end
|
|
$var wire 314 EG! head_r [313:0] $end
|
|
$var wire 2 9I! rd_ptr_next_r [1:0] $end
|
|
$var wire 2 1I! rd_ptr_r [1:0] $end
|
|
$var wire 2 )I! wr_ptr_r [1:0] $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope module sel_bank $end
|
|
$var wire 32 on" N [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 2 /: grant_index [1:0] $end
|
|
$var wire 4 kD grant_onehot [3:0] $end
|
|
$var wire 1 ': grant_valid $end
|
|
$var wire 4 kB! requests [3:0] $end
|
|
$var wire 1 [h" reset $end
|
|
$scope module genblk2 $end
|
|
$var wire 4 kD grant_onehot_r [3:0] $end
|
|
$scope module priority_encoder $end
|
|
$var wire 32 on" N [31:0] $end
|
|
$var wire 4 kB! data_in [3:0] $end
|
|
$var wire 2 /: data_out [1:0] $end
|
|
$var wire 32 sD i [31:0] $end
|
|
$var wire 1 ': valid_out $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope module cwb_queue $end
|
|
$var wire 32 wn" BUFFERED_OUTPUT [31:0] $end
|
|
$var wire 32 ;p" DATAW [31:0] $end
|
|
$var wire 32 on" SIZE [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 76 aK data_in [75:0] $end
|
|
$var wire 76 yK data_out [75:0] $end
|
|
$var wire 1 [6! empty $end
|
|
$var wire 1 c6! full $end
|
|
$var wire 1 ?* pop $end
|
|
$var wire 1 {@ push $end
|
|
$var wire 1 q# reading $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 3 iQ! size [2:0] $end
|
|
$var wire 3 iQ! size_r [2:0] $end
|
|
$var wire 1 3L writing $end
|
|
$scope module genblk3 $end
|
|
$var wire 76 qQ! data(0) [75:0] $end
|
|
$var wire 76 tQ! data(1) [75:0] $end
|
|
$var wire 76 wQ! data(2) [75:0] $end
|
|
$var wire 76 zQ! data(3) [75:0] $end
|
|
$scope module genblk2 $end
|
|
$var wire 1 ]S! bypass_r $end
|
|
$var wire 76 -S! curr_r [75:0] $end
|
|
$var wire 1 [6! empty_r $end
|
|
$var wire 1 c6! full_r $end
|
|
$var wire 76 sR! head_r [75:0] $end
|
|
$var wire 2 US! rd_ptr_next_r [1:0] $end
|
|
$var wire 2 MS! rd_ptr_r [1:0] $end
|
|
$var wire 2 ES! wr_ptr_r [1:0] $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope module dfp_queue $end
|
|
$var wire 32 wn" BUFFERED_OUTPUT [31:0] $end
|
|
$var wire 32 qo" DATAW [31:0] $end
|
|
$var wire 32 gn" SIZE [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 154 G" data_in [153:0] $end
|
|
$var wire 154 }A data_out [153:0] $end
|
|
$var wire 1 {2! empty $end
|
|
$var wire 1 %3! full $end
|
|
$var wire 1 E9 pop $end
|
|
$var wire 1 Um" push $end
|
|
$var wire 1 GB reading $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 5 c:! size [4:0] $end
|
|
$var wire 5 c:! size_r [4:0] $end
|
|
$var wire 1 o" writing $end
|
|
$scope module genblk3 $end
|
|
$var wire 154 k:! data(0) [153:0] $end
|
|
$var wire 154 p:! data(1) [153:0] $end
|
|
$var wire 154 ?;! data(10) [153:0] $end
|
|
$var wire 154 D;! data(11) [153:0] $end
|
|
$var wire 154 I;! data(12) [153:0] $end
|
|
$var wire 154 N;! data(13) [153:0] $end
|
|
$var wire 154 S;! data(14) [153:0] $end
|
|
$var wire 154 X;! data(15) [153:0] $end
|
|
$var wire 154 u:! data(2) [153:0] $end
|
|
$var wire 154 z:! data(3) [153:0] $end
|
|
$var wire 154 !;! data(4) [153:0] $end
|
|
$var wire 154 &;! data(5) [153:0] $end
|
|
$var wire 154 +;! data(6) [153:0] $end
|
|
$var wire 154 0;! data(7) [153:0] $end
|
|
$var wire 154 5;! data(8) [153:0] $end
|
|
$var wire 154 :;! data(9) [153:0] $end
|
|
$scope module genblk2 $end
|
|
$var wire 1 cB! bypass_r $end
|
|
$var wire 154 #B! curr_r [153:0] $end
|
|
$var wire 1 {2! empty_r $end
|
|
$var wire 1 %3! full_r $end
|
|
$var wire 154 YA! head_r [153:0] $end
|
|
$var wire 4 [B! rd_ptr_next_r [3:0] $end
|
|
$var wire 4 SB! rd_ptr_r [3:0] $end
|
|
$var wire 4 KB! wr_ptr_r [3:0] $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope module dwb_queue $end
|
|
$var wire 32 wn" BUFFERED_OUTPUT [31:0] $end
|
|
$var wire 32 Cp" DATAW [31:0] $end
|
|
$var wire 32 on" SIZE [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 200 ;L data_in [199:0] $end
|
|
$var wire 200 sL data_out [199:0] $end
|
|
$var wire 1 k6! empty $end
|
|
$var wire 1 s6! full $end
|
|
$var wire 1 G* pop $end
|
|
$var wire 1 5A push $end
|
|
$var wire 1 y# reading $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 3 eS! size [2:0] $end
|
|
$var wire 3 eS! size_r [2:0] $end
|
|
$var wire 1 MM writing $end
|
|
$scope module genblk3 $end
|
|
$var wire 200 mS! data(0) [199:0] $end
|
|
$var wire 200 tS! data(1) [199:0] $end
|
|
$var wire 200 {S! data(2) [199:0] $end
|
|
$var wire 200 $T! data(3) [199:0] $end
|
|
$scope module genblk2 $end
|
|
$var wire 1 ]W! bypass_r $end
|
|
$var wire 200 kV! curr_r [199:0] $end
|
|
$var wire 1 k6! empty_r $end
|
|
$var wire 1 s6! full_r $end
|
|
$var wire 200 3V! head_r [199:0] $end
|
|
$var wire 2 UW! rd_ptr_next_r [1:0] $end
|
|
$var wire 2 MW! rd_ptr_r [1:0] $end
|
|
$var wire 2 EW! wr_ptr_r [1:0] $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope module s0_1_c0 $end
|
|
$var wire 32 #p" N [31:0] $end
|
|
$var wire 32 Wn" PASSTHRU [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 1 Io" flush $end
|
|
$var wire 243 {D in [242:0] $end
|
|
$var wire 243 II! out [242:0] $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 1 Q; stall $end
|
|
$var wire 243 II! value [242:0] $end
|
|
$upscope $end
|
|
$scope module snp_req_queue $end
|
|
$var wire 32 wn" BUFFERED_OUTPUT [31:0] $end
|
|
$var wire 32 io" DATAW [31:0] $end
|
|
$var wire 32 gn" SIZE [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 55 /" data_in [54:0] $end
|
|
$var wire 55 eA data_out [54:0] $end
|
|
$var wire 1 k2! empty $end
|
|
$var wire 1 s2! full $end
|
|
$var wire 1 %9 pop $end
|
|
$var wire 1 em" push $end
|
|
$var wire 1 uA reading $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 5 57! size [4:0] $end
|
|
$var wire 5 57! size_r [4:0] $end
|
|
$var wire 1 ?" writing $end
|
|
$scope module genblk3 $end
|
|
$var wire 55 =7! data(0) [54:0] $end
|
|
$var wire 55 ?7! data(1) [54:0] $end
|
|
$var wire 55 Q7! data(10) [54:0] $end
|
|
$var wire 55 S7! data(11) [54:0] $end
|
|
$var wire 55 U7! data(12) [54:0] $end
|
|
$var wire 55 W7! data(13) [54:0] $end
|
|
$var wire 55 Y7! data(14) [54:0] $end
|
|
$var wire 55 [7! data(15) [54:0] $end
|
|
$var wire 55 A7! data(2) [54:0] $end
|
|
$var wire 55 C7! data(3) [54:0] $end
|
|
$var wire 55 E7! data(4) [54:0] $end
|
|
$var wire 55 G7! data(5) [54:0] $end
|
|
$var wire 55 I7! data(6) [54:0] $end
|
|
$var wire 55 K7! data(7) [54:0] $end
|
|
$var wire 55 M7! data(8) [54:0] $end
|
|
$var wire 55 O7! data(9) [54:0] $end
|
|
$scope module genblk2 $end
|
|
$var wire 1 [:! bypass_r $end
|
|
$var wire 55 3:! curr_r [54:0] $end
|
|
$var wire 1 k2! empty_r $end
|
|
$var wire 1 s2! full_r $end
|
|
$var wire 55 #:! head_r [54:0] $end
|
|
$var wire 4 S:! rd_ptr_next_r [3:0] $end
|
|
$var wire 4 K:! rd_ptr_r [3:0] $end
|
|
$var wire 4 C:! wr_ptr_r [3:0] $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope module st_1e_2 $end
|
|
$var wire 32 3p" N [31:0] $end
|
|
$var wire 32 Wn" PASSTHRU [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 1 Io" flush $end
|
|
$var wire 316 'J in [315:0] $end
|
|
$var wire 316 -K! out [315:0] $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 1 Q; stall $end
|
|
$var wire 316 -K! value [315:0] $end
|
|
$upscope $end
|
|
$scope module tag_data_access $end
|
|
$var wire 32 gn" BANK_LINE_SIZE [31:0] $end
|
|
$var wire 32 _n" CACHE_SIZE [31:0] $end
|
|
$var wire 32 wn" DRAM_ENABLE [31:0] $end
|
|
$var wire 32 on" NUM_BANKS [31:0] $end
|
|
$var wire 32 wn" STAGE_1_CYCLES [31:0] $end
|
|
$var wire 32 on" WORD_SIZE [31:0] $end
|
|
$var wire 32 wn" WRITE_ENABLE [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 128 yG data_write [127:0] $end
|
|
$var wire 1 w> dirty_st1e $end
|
|
$var wire 16 !? dirtyb_st1e [15:0] $end
|
|
$var wire 1 Q? fill_saw_dirty_st1e $end
|
|
$var wire 1 o> fill_sent $end
|
|
$var wire 1 %I force_core_miss $end
|
|
$var wire 1 !; force_request_miss_st1e $end
|
|
$var wire 1 ;H invalidate_line $end
|
|
$var wire 1 Y? is_snp_st1e $end
|
|
$var wire 4 I? mem_byteen_st1e [3:0] $end
|
|
$var wire 1 A? mem_rw_st1e $end
|
|
$var wire 1 o> miss_st1e $end
|
|
$var wire 1 q? mrvq_init_ready_state_st1e $end
|
|
$var wire 128 AG qual_read_data_st1 [127:0] $end
|
|
$var wire 1 )G qual_read_dirty_st1 $end
|
|
$var wire 16 1G qual_read_dirtyb_st1 [15:0] $end
|
|
$var wire 20 9G qual_read_tag_st1 [19:0] $end
|
|
$var wire 1 !G qual_read_valid_st1 $end
|
|
$var wire 128 _F read_data_st1c(0) [127:0] $end
|
|
$var wire 1 GF read_dirty_st1c(0) $end
|
|
$var wire 16 OF read_dirtyb_st1c(0) [15:0] $end
|
|
$var wire 20 WF read_tag_st1c(0) [19:0] $end
|
|
$var wire 1 ?F read_valid_st1c(0) $end
|
|
$var wire 6 ]E readaddr_st10 [5:0] $end
|
|
$var wire 128 G> readdata_st1e [127:0] $end
|
|
$var wire 20 g> readtag_st1e [19:0] $end
|
|
$var wire 32 ?> readword_st1e [31:0] $end
|
|
$var wire 1 {H real_miss $end
|
|
$var wire 1 KH real_writefill $end
|
|
$var wire 1 kH req_invalid $end
|
|
$var wire 1 sH req_miss $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 1 cH should_write $end
|
|
$var wire 1 ;H snoop_hit_no_pending $end
|
|
$var wire 1 a? snp_invalidate_st1e $end
|
|
$var wire 1 i? snp_to_mrvq_st1e $end
|
|
$var wire 1 Q; stall $end
|
|
$var wire 1 Q; stall_bank_pipe $end
|
|
$var wire 1 CH tags_match $end
|
|
$var wire 128 G> use_read_data_st1e [127:0] $end
|
|
$var wire 1 iG use_read_dirty_st1e $end
|
|
$var wire 16 !? use_read_dirtyb_st1e [15:0] $end
|
|
$var wire 20 g> use_read_tag_st1e [19:0] $end
|
|
$var wire 1 aG use_read_valid_st1e $end
|
|
$var wire 128 yG use_write_data [127:0] $end
|
|
$var wire 16 qG use_write_enable [15:0] $end
|
|
$var wire 1 #@ valid_req_st1e $end
|
|
$var wire 16 [H we [15:0] $end
|
|
$var wire 2 7F wordsel_st1e [1:0] $end
|
|
$var wire 26 ;@ writeaddr_st1e [25:0] $end
|
|
$var wire 128 uE writedata_st1e [127:0] $end
|
|
$var wire 1 eE writefill_st1e $end
|
|
$var wire 6 ]E writeladdr_st1e [5:0] $end
|
|
$var wire 20 SH writetag_st1e [19:0] $end
|
|
$var wire 32 mE writeword_st1e [31:0] $end
|
|
$scope module genblk4(0) $end
|
|
$var wire 1 -I normal_write $end
|
|
$upscope $end
|
|
$scope module genblk4(1) $end
|
|
$var wire 1 5I normal_write $end
|
|
$upscope $end
|
|
$scope module genblk4(2) $end
|
|
$var wire 1 =I normal_write $end
|
|
$upscope $end
|
|
$scope module genblk4(3) $end
|
|
$var wire 1 EI normal_write $end
|
|
$upscope $end
|
|
$scope module s0_1_c0 $end
|
|
$var wire 32 +p" N [31:0] $end
|
|
$var wire 32 wn" PASSTHRU [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 1 Io" flush $end
|
|
$var wire 166 UI in [165:0] $end
|
|
$var wire 166 UI out [165:0] $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 1 Q; stall $end
|
|
$var wire 166 [J! value [165:0] $end
|
|
$upscope $end
|
|
$scope module tag_data_structure $end
|
|
$var wire 32 gn" BANK_LINE_SIZE [31:0] $end
|
|
$var wire 32 _n" CACHE_SIZE [31:0] $end
|
|
$var wire 32 on" NUM_BANKS [31:0] $end
|
|
$var wire 32 on" WORD_SIZE [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 64 +J! dirty [63:0] $end
|
|
$var wire 1 MI do_write $end
|
|
$var wire 1 o> fill_sent $end
|
|
$var wire 32 KJ! i [31:0] $end
|
|
$var wire 1 ;H invalidate $end
|
|
$var wire 32 SJ! j [31:0] $end
|
|
$var wire 6 ]E read_addr [5:0] $end
|
|
$var wire 128 AG read_data [127:0] $end
|
|
$var wire 1 )G read_dirty $end
|
|
$var wire 16 1G read_dirtyb [15:0] $end
|
|
$var wire 20 9G read_tag [19:0] $end
|
|
$var wire 1 !G read_valid $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 1 Q; stall_bank_pipe $end
|
|
$var wire 20 SH tag_index [19:0] $end
|
|
$var wire 64 ;J! valid [63:0] $end
|
|
$var wire 6 ]E write_addr [5:0] $end
|
|
$var wire 128 yG write_data [127:0] $end
|
|
$var wire 16 qG write_enable [15:0] $end
|
|
$var wire 1 KH write_fill $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope module genblk5(1) $end
|
|
$var wire 120 {h" curr_bank_core_req_addr [119:0] $end
|
|
$var wire 16 sh" curr_bank_core_req_byteen [15:0] $end
|
|
$var wire 128 =i" curr_bank_core_req_data [127:0] $end
|
|
$var wire 1 y-! curr_bank_core_req_ready $end
|
|
$var wire 4 kh" curr_bank_core_req_rw [3:0] $end
|
|
$var wire 42 ]i" curr_bank_core_req_tag [41:0] $end
|
|
$var wire 4 c curr_bank_core_req_valid [3:0] $end
|
|
$var wire 32 {0 curr_bank_core_rsp_data [31:0] $end
|
|
$var wire 1 k curr_bank_core_rsp_ready $end
|
|
$var wire 42 %1 curr_bank_core_rsp_tag [41:0] $end
|
|
$var wire 2 s0 curr_bank_core_rsp_tid [1:0] $end
|
|
$var wire 1 Y-! curr_bank_core_rsp_valid $end
|
|
$var wire 26 i-! curr_bank_dram_fill_req_addr [25:0] $end
|
|
$var wire 1 )-! curr_bank_dram_fill_req_ready $end
|
|
$var wire 1 51 curr_bank_dram_fill_req_valid $end
|
|
$var wire 26 ]m" curr_bank_dram_fill_rsp_addr [25:0] $end
|
|
$var wire 128 Qk" curr_bank_dram_fill_rsp_data [127:0] $end
|
|
$var wire 1 a-! curr_bank_dram_fill_rsp_ready $end
|
|
$var wire 1 um" curr_bank_dram_fill_rsp_valid $end
|
|
$var wire 26 M1 curr_bank_dram_wb_req_addr [25:0] $end
|
|
$var wire 16 E1 curr_bank_dram_wb_req_byteen [15:0] $end
|
|
$var wire 128 U1 curr_bank_dram_wb_req_data [127:0] $end
|
|
$var wire 1 s curr_bank_dram_wb_req_ready $end
|
|
$var wire 1 =1 curr_bank_dram_wb_req_valid $end
|
|
$var wire 26 mm" curr_bank_snp_req_addr [25:0] $end
|
|
$var wire 1 3l" curr_bank_snp_req_invalidate $end
|
|
$var wire 1 q-! curr_bank_snp_req_ready $end
|
|
$var wire 28 ;l" curr_bank_snp_req_tag [27:0] $end
|
|
$var wire 1 }m" curr_bank_snp_req_valid $end
|
|
$var wire 1 { curr_bank_snp_rsp_ready $end
|
|
$var wire 28 }1 curr_bank_snp_rsp_tag [27:0] $end
|
|
$var wire 1 u1 curr_bank_snp_rsp_valid $end
|
|
$scope module bank $end
|
|
$var wire 32 ao" BANK_ID [31:0] $end
|
|
$var wire 32 gn" BANK_LINE_SIZE [31:0] $end
|
|
$var wire 32 Wn" CACHE_ID [31:0] $end
|
|
$var wire 32 _n" CACHE_SIZE [31:0] $end
|
|
$var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end
|
|
$var wire 32 !o" CORE_TAG_WIDTH [31:0] $end
|
|
$var wire 32 on" CREQ_SIZE [31:0] $end
|
|
$var wire 32 on" CWBQ_SIZE [31:0] $end
|
|
$var wire 32 gn" DFPQ_SIZE [31:0] $end
|
|
$var wire 32 on" DFQQ_SIZE [31:0] $end
|
|
$var wire 32 wn" DRAM_ENABLE [31:0] $end
|
|
$var wire 32 on" DWBQ_SIZE [31:0] $end
|
|
$var wire 32 gn" MRVQ_SIZE [31:0] $end
|
|
$var wire 32 on" NUM_BANKS [31:0] $end
|
|
$var wire 32 on" NUM_REQUESTS [31:0] $end
|
|
$var wire 32 Wn" SNOOP_FORWARDING [31:0] $end
|
|
$var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end
|
|
$var wire 32 gn" SNRQ_SIZE [31:0] $end
|
|
$var wire 32 wn" STAGE_1_CYCLES [31:0] $end
|
|
$var wire 32 on" WORD_SIZE [31:0] $end
|
|
$var wire 32 wn" WRITE_ENABLE [31:0] $end
|
|
$var wire 26 mQ addr_st1(0) [25:0] $end
|
|
$var wire 26 kT addr_st1e [25:0] $end
|
|
$var wire 26 i-! addr_st2 [25:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 120 {h" core_req_addr [119:0] $end
|
|
$var wire 16 sh" core_req_byteen [15:0] $end
|
|
$var wire 128 =i" core_req_data [127:0] $end
|
|
$var wire 1 y-! core_req_ready $end
|
|
$var wire 4 kh" core_req_rw [3:0] $end
|
|
$var wire 42 ]i" core_req_tag [41:0] $end
|
|
$var wire 4 c core_req_valid [3:0] $end
|
|
$var wire 32 {0 core_rsp_data [31:0] $end
|
|
$var wire 1 k core_rsp_ready $end
|
|
$var wire 42 %1 core_rsp_tag [41:0] $end
|
|
$var wire 2 s0 core_rsp_tid [1:0] $end
|
|
$var wire 1 Y-! core_rsp_valid $end
|
|
$var wire 32 #Z! cwbq_data [31:0] $end
|
|
$var wire 1 U[! cwbq_empty $end
|
|
$var wire 1 ][! cwbq_full $end
|
|
$var wire 1 _* cwbq_pop $end
|
|
$var wire 1 MU cwbq_push $end
|
|
$var wire 1 iO cwbq_push_stall $end
|
|
$var wire 1 UU cwbq_push_unqual $end
|
|
$var wire 42 AY! cwbq_tag [41:0] $end
|
|
$var wire 2 9Y! cwbq_tid [1:0] $end
|
|
$var wire 26 }M dfpq_addr_st0 [25:0] $end
|
|
$var wire 1 uW! dfpq_empty $end
|
|
$var wire 128 'N dfpq_filldata_st0 [127:0] $end
|
|
$var wire 1 }W! dfpq_full $end
|
|
$var wire 1 uM dfpq_pop $end
|
|
$var wire 1 CP dfpq_pop_unqual $end
|
|
$var wire 1 IS dirty_st1e $end
|
|
$var wire 1 SZ! dirty_st2 $end
|
|
$var wire 16 QS dirtyb_st1e [15:0] $end
|
|
$var wire 16 [Z! dirtyb_st2 [15:0] $end
|
|
$var wire 26 i-! dram_fill_req_addr [25:0] $end
|
|
$var wire 1 5U dram_fill_req_fast $end
|
|
$var wire 1 )-! dram_fill_req_ready $end
|
|
$var wire 1 yO dram_fill_req_stall $end
|
|
$var wire 1 ]U dram_fill_req_unqual $end
|
|
$var wire 1 51 dram_fill_req_valid $end
|
|
$var wire 26 ]m" dram_fill_rsp_addr [25:0] $end
|
|
$var wire 128 Qk" dram_fill_rsp_data [127:0] $end
|
|
$var wire 1 a-! dram_fill_rsp_ready $end
|
|
$var wire 1 um" dram_fill_rsp_valid $end
|
|
$var wire 26 M1 dram_wb_req_addr [25:0] $end
|
|
$var wire 16 E1 dram_wb_req_byteen [15:0] $end
|
|
$var wire 128 U1 dram_wb_req_data [127:0] $end
|
|
$var wire 1 #$ dram_wb_req_fire $end
|
|
$var wire 1 s dram_wb_req_ready $end
|
|
$var wire 1 =1 dram_wb_req_valid $end
|
|
$var wire 1 '\! dwbq_dual_valid_sel $end
|
|
$var wire 1 e[! dwbq_empty $end
|
|
$var wire 1 m[! dwbq_full $end
|
|
$var wire 1 mU dwbq_is_dwb_in $end
|
|
$var wire 1 }U dwbq_is_dwb_out $end
|
|
$var wire 1 uU dwbq_is_snp_in $end
|
|
$var wire 1 'V dwbq_is_snp_out $end
|
|
$var wire 1 g* dwbq_pop $end
|
|
$var wire 1 eU dwbq_push $end
|
|
$var wire 1 qO dwbq_push_stall $end
|
|
$var wire 1 /V dwbq_push_unqual $end
|
|
$var wire 26 u[! dwbq_req_addr [25:0] $end
|
|
$var wire 1 #T fill_saw_dirty_st1e $end
|
|
$var wire 1 {Z! fill_saw_dirty_st2 $end
|
|
$var wire 1 QO force_request_miss_st1e $end
|
|
$var wire 1 ;P going_to_write_st1(0) $end
|
|
$var wire 49 'R inst_meta_st1(0) [48:0] $end
|
|
$var wire 49 cZ! inst_meta_st2 [48:0] $end
|
|
$var wire 1 +P is_fill_in_pipe $end
|
|
$var wire 1 3P is_fill_st1(0) $end
|
|
$var wire 1 aY! is_fill_st2 $end
|
|
$var wire 1 gR is_mrvq_st1(0) $end
|
|
$var wire 1 [T is_mrvq_st1e $end
|
|
$var wire 1 [T is_mrvq_st1e_st2 $end
|
|
$var wire 1 =[! is_mrvq_st2 $end
|
|
$var wire 1 WR is_snp_st1(0) $end
|
|
$var wire 1 +T is_snp_st1e $end
|
|
$var wire 1 %[! is_snp_st2 $end
|
|
$var wire 32 ao" j [31:0] $end
|
|
$var wire 4 yS mem_byteen_st1e [3:0] $end
|
|
$var wire 1 qS mem_rw_st1e $end
|
|
$var wire 1 =U miss_add $end
|
|
$var wire 26 i-! miss_add_addr [25:0] $end
|
|
$var wire 1 KT miss_add_because_miss $end
|
|
$var wire 1 5[! miss_add_because_pending $end
|
|
$var wire 4 YY! miss_add_byteen [3:0] $end
|
|
$var wire 32 yY! miss_add_data [31:0] $end
|
|
$var wire 1 EU miss_add_is_mrvq $end
|
|
$var wire 1 %[! miss_add_is_snp $end
|
|
$var wire 1 QY! miss_add_rw $end
|
|
$var wire 1 -[! miss_add_snp_invalidate $end
|
|
$var wire 42 AY! miss_add_tag [41:0] $end
|
|
$var wire 2 9Y! miss_add_tid [1:0] $end
|
|
$var wire 1 5U miss_add_unqual $end
|
|
$var wire 2 qY! miss_add_wsel [1:0] $end
|
|
$var wire 1 AS miss_st1e $end
|
|
$var wire 1 KZ! miss_st2 $end
|
|
$var wire 26 WX! mrvq_addr_st0 [25:0] $end
|
|
$var wire 4 !Y! mrvq_byteen_st0 [3:0] $end
|
|
$var wire 1 ?X! mrvq_full $end
|
|
$var wire 1 %U mrvq_init_ready_state_hazard_st0_st1 $end
|
|
$var wire 1 -U mrvq_init_ready_state_hazard_st1e_st1 $end
|
|
$var wire 1 CT mrvq_init_ready_state_st1e $end
|
|
$var wire 1 {T mrvq_init_ready_state_st2 $end
|
|
$var wire 1 M[! mrvq_init_ready_state_unqual_st2 $end
|
|
$var wire 1 )Y! mrvq_is_snp_st0 $end
|
|
$var wire 1 AO mrvq_pending_hazard_st1e $end
|
|
$var wire 1 )O mrvq_pop $end
|
|
$var wire 1 1O mrvq_pop_unqual $end
|
|
$var wire 1 aO mrvq_push_stall $end
|
|
$var wire 1 cT mrvq_recover_ready_state_st1e $end
|
|
$var wire 1 E[! mrvq_recover_ready_state_st2 $end
|
|
$var wire 1 9O mrvq_rw_st0 $end
|
|
$var wire 1 1Y! mrvq_snp_invalidate_st0 $end
|
|
$var wire 1 GX! mrvq_stop $end
|
|
$var wire 42 oX! mrvq_tag_st0 [41:0] $end
|
|
$var wire 2 OX! mrvq_tid_st0 [1:0] $end
|
|
$var wire 1 1O mrvq_valid_st0 $end
|
|
$var wire 32 gX! mrvq_writeword_st0 [31:0] $end
|
|
$var wire 2 _X! mrvq_wsel_st0 [1:0] $end
|
|
$var wire 26 cP qual_addr_st0 [25:0] $end
|
|
$var wire 1 MQ qual_going_to_write_st0 $end
|
|
$var wire 49 =Q qual_inst_meta_st0 [48:0] $end
|
|
$var wire 1 CP qual_is_fill_st0 $end
|
|
$var wire 1 1O qual_is_mrvq_st0 $end
|
|
$var wire 1 UQ qual_is_snp_st0 $end
|
|
$var wire 1 ]Q qual_snp_invalidate_st0 $end
|
|
$var wire 1 [P qual_valid_st0 $end
|
|
$var wire 1 sT qual_valid_st1e_2 $end
|
|
$var wire 128 {P qual_writedata_st0 [127:0] $end
|
|
$var wire 32 sP qual_writeword_st0 [31:0] $end
|
|
$var wire 2 kP qual_wsel_st0 [1:0] $end
|
|
$var wire 128 wR readdata_st1e [127:0] $end
|
|
$var wire 128 +Z! readdata_st2 [127:0] $end
|
|
$var wire 20 9S readtag_st1e [19:0] $end
|
|
$var wire 20 sZ! readtag_st2 [19:0] $end
|
|
$var wire 32 oR readword_st1e [31:0] $end
|
|
$var wire 32 #Z! readword_st2 [31:0] $end
|
|
$var wire 1 YO recover_mrvq_state_st2 $end
|
|
$var wire 1 ON reqq_empty $end
|
|
$var wire 1 'X! reqq_full $end
|
|
$var wire 1 GN reqq_pop $end
|
|
$var wire 1 KP reqq_pop_unqual $end
|
|
$var wire 1 W* reqq_push $end
|
|
$var wire 30 wN reqq_req_addr_st0 [29:0] $end
|
|
$var wire 4 oN reqq_req_byteen_st0 [3:0] $end
|
|
$var wire 1 gN reqq_req_rw_st0 $end
|
|
$var wire 1 WN reqq_req_st0 $end
|
|
$var wire 42 /X! reqq_req_tag_st0 [41:0] $end
|
|
$var wire 2 _N reqq_req_tid_st0 [1:0] $end
|
|
$var wire 32 !O reqq_req_writeword_st0 [31:0] $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 1 _R snp_invalidate_st1(0) $end
|
|
$var wire 1 3T snp_invalidate_st1e $end
|
|
$var wire 1 -[! snp_invalidate_st2 $end
|
|
$var wire 26 mm" snp_req_addr [25:0] $end
|
|
$var wire 1 3l" snp_req_invalidate $end
|
|
$var wire 1 q-! snp_req_ready $end
|
|
$var wire 28 ;l" snp_req_tag [27:0] $end
|
|
$var wire 1 }m" snp_req_valid $end
|
|
$var wire 1 +$ snp_rsp_fire $end
|
|
$var wire 1 { snp_rsp_ready $end
|
|
$var wire 28 }1 snp_rsp_tag [27:0] $end
|
|
$var wire 1 u1 snp_rsp_valid $end
|
|
$var wire 1 ;T snp_to_mrvq_st1e $end
|
|
$var wire 1 5[! snp_to_mrvq_st2 $end
|
|
$var wire 26 ]M snrq_addr_st0 [25:0] $end
|
|
$var wire 1 eW! snrq_empty $end
|
|
$var wire 1 mW! snrq_full $end
|
|
$var wire 1 eM snrq_invalidate_st0 $end
|
|
$var wire 1 UM snrq_pop $end
|
|
$var wire 1 SP snrq_pop_unqual $end
|
|
$var wire 28 mM snrq_tag_st0 [27:0] $end
|
|
$var wire 28 }[! snrq_tag_st2 [27:0] $end
|
|
$var wire 1 IO st2_pending_hazard_st1e $end
|
|
$var wire 1 #P stall_bank_pipe $end
|
|
$var wire 42 YS tag_st1e [41:0] $end
|
|
$var wire 2 iS tid_st1e [1:0] $end
|
|
$var wire 1 eQ valid_st1(0) $end
|
|
$var wire 1 ST valid_st1e $end
|
|
$var wire 1 iY! valid_st2 $end
|
|
$var wire 128 7R writedata_st1(0) [127:0] $end
|
|
$var wire 32 }Q writeword_st1(0) [31:0] $end
|
|
$var wire 32 yY! writeword_st2 [31:0] $end
|
|
$var wire 2 uQ wsel_st1(0) [1:0] $end
|
|
$var wire 2 qY! wsel_st2 [1:0] $end
|
|
$scope module cache_miss_resrv $end
|
|
$var wire 32 ao" BANK_ID [31:0] $end
|
|
$var wire 32 gn" BANK_LINE_SIZE [31:0] $end
|
|
$var wire 32 Wn" CACHE_ID [31:0] $end
|
|
$var wire 32 !o" CORE_TAG_WIDTH [31:0] $end
|
|
$var wire 32 gn" MRVQ_SIZE [31:0] $end
|
|
$var wire 32 on" NUM_BANKS [31:0] $end
|
|
$var wire 32 on" NUM_REQUESTS [31:0] $end
|
|
$var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end
|
|
$var wire 32 on" WORD_SIZE [31:0] $end
|
|
$var wire 416 !u! addr_table [415:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 4 ;v! dequeue_index [3:0] $end
|
|
$var wire 1 1O dequeue_possible $end
|
|
$var wire 4 Kv! enqueue_index [3:0] $end
|
|
$var wire 1 [v! enqueue_possible $end
|
|
$var wire 26 kT fill_addr_st1 [25:0] $end
|
|
$var wire 4 Cv! head_ptr [3:0] $end
|
|
$var wire 1 y_ increment_head $end
|
|
$var wire 1 7Z is_fill_st1 $end
|
|
$var wire 1 EU is_mrvq $end
|
|
$var wire 16 I_ make_ready [15:0] $end
|
|
$var wire 16 Q_ make_ready_push [15:0] $end
|
|
$var wire 85 wp! metadata_table(0) [84:0] $end
|
|
$var wire 85 zp! metadata_table(1) [84:0] $end
|
|
$var wire 85 7q! metadata_table(10) [84:0] $end
|
|
$var wire 85 :q! metadata_table(11) [84:0] $end
|
|
$var wire 85 =q! metadata_table(12) [84:0] $end
|
|
$var wire 85 @q! metadata_table(13) [84:0] $end
|
|
$var wire 85 Cq! metadata_table(14) [84:0] $end
|
|
$var wire 85 Fq! metadata_table(15) [84:0] $end
|
|
$var wire 85 }p! metadata_table(2) [84:0] $end
|
|
$var wire 85 "q! metadata_table(3) [84:0] $end
|
|
$var wire 85 %q! metadata_table(4) [84:0] $end
|
|
$var wire 85 (q! metadata_table(5) [84:0] $end
|
|
$var wire 85 +q! metadata_table(6) [84:0] $end
|
|
$var wire 85 .q! metadata_table(7) [84:0] $end
|
|
$var wire 85 1q! metadata_table(8) [84:0] $end
|
|
$var wire 85 4q! metadata_table(9) [84:0] $end
|
|
$var wire 1 =U miss_add $end
|
|
$var wire 26 i-! miss_add_addr [25:0] $end
|
|
$var wire 4 YY! miss_add_byteen [3:0] $end
|
|
$var wire 32 yY! miss_add_data [31:0] $end
|
|
$var wire 1 %[! miss_add_is_snp $end
|
|
$var wire 1 QY! miss_add_rw $end
|
|
$var wire 1 -[! miss_add_snp_invalidate $end
|
|
$var wire 42 AY! miss_add_tag [41:0] $end
|
|
$var wire 2 9Y! miss_add_tid [1:0] $end
|
|
$var wire 2 qY! miss_add_wsel [1:0] $end
|
|
$var wire 26 WX! miss_resrv_addr_st0 [25:0] $end
|
|
$var wire 4 !Y! miss_resrv_byteen_st0 [3:0] $end
|
|
$var wire 32 gX! miss_resrv_data_st0 [31:0] $end
|
|
$var wire 1 ?X! miss_resrv_full $end
|
|
$var wire 1 )Y! miss_resrv_is_snp_st0 $end
|
|
$var wire 1 )O miss_resrv_pop $end
|
|
$var wire 1 9O miss_resrv_rw_st0 $end
|
|
$var wire 1 1Y! miss_resrv_snp_invalidate_st0 $end
|
|
$var wire 1 GX! miss_resrv_stop $end
|
|
$var wire 42 oX! miss_resrv_tag_st0 [41:0] $end
|
|
$var wire 2 OX! miss_resrv_tid_st0 [1:0] $end
|
|
$var wire 1 1O miss_resrv_valid_st0 $end
|
|
$var wire 2 _X! miss_resrv_wsel_st0 [1:0] $end
|
|
$var wire 1 {T mrvq_init_ready_state $end
|
|
$var wire 1 i_ mrvq_pop $end
|
|
$var wire 1 a_ mrvq_push $end
|
|
$var wire 1 AO pending_hazard $end
|
|
$var wire 1 +` qual_mrvq_init $end
|
|
$var wire 16 3v! ready_table [15:0] $end
|
|
$var wire 1 q_ recover_state $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 4 ;v! schedule_ptr [3:0] $end
|
|
$var wire 5 Sv! size [4:0] $end
|
|
$var wire 4 Kv! tail_ptr [3:0] $end
|
|
$var wire 1 #` update_ready $end
|
|
$var wire 16 Y_ valid_address_match [15:0] $end
|
|
$var wire 16 +v! valid_table [15:0] $end
|
|
$upscope $end
|
|
$scope module core_req_arb $end
|
|
$var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end
|
|
$var wire 32 !o" CORE_TAG_WIDTH [31:0] $end
|
|
$var wire 32 on" CREQ_SIZE [31:0] $end
|
|
$var wire 32 on" NUM_REQUESTS [31:0] $end
|
|
$var wire 32 on" WORD_SIZE [31:0] $end
|
|
$var wire 120 {h" bank_addr [119:0] $end
|
|
$var wire 16 sh" bank_byteen [15:0] $end
|
|
$var wire 4 kh" bank_rw [3:0] $end
|
|
$var wire 42 ]i" bank_tag [41:0] $end
|
|
$var wire 4 c bank_valids [3:0] $end
|
|
$var wire 128 =i" bank_writedata [127:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 1 _h! o_empty $end
|
|
$var wire 1 +X out_empty $end
|
|
$var wire 120 9W out_per_addr [119:0] $end
|
|
$var wire 16 1W out_per_byteen [15:0] $end
|
|
$var wire 4 )W out_per_rw [3:0] $end
|
|
$var wire 42 yW out_per_tag [41:0] $end
|
|
$var wire 4 !W out_per_valids [3:0] $end
|
|
$var wire 128 YW out_per_writedata [127:0] $end
|
|
$var wire 1 3X pop_qual $end
|
|
$var wire 1 o* push_qual $end
|
|
$var wire 120 }g! qual_addr [119:0] $end
|
|
$var wire 16 ug! qual_byteen [15:0] $end
|
|
$var wire 1 WN qual_has_request $end
|
|
$var wire 2 _N qual_request_index [1:0] $end
|
|
$var wire 4 mg! qual_rw [3:0] $end
|
|
$var wire 42 /X! qual_tag [41:0] $end
|
|
$var wire 4 eg! qual_valids [3:0] $end
|
|
$var wire 128 ?h! qual_writedata [127:0] $end
|
|
$var wire 4 ;X real_out_per_valids [3:0] $end
|
|
$var wire 1 ON reqq_empty $end
|
|
$var wire 1 'X! reqq_full $end
|
|
$var wire 1 GN reqq_pop $end
|
|
$var wire 1 W* reqq_push $end
|
|
$var wire 30 wN reqq_req_addr_st0 [29:0] $end
|
|
$var wire 4 oN reqq_req_byteen_st0 [3:0] $end
|
|
$var wire 1 gN reqq_req_rw_st0 $end
|
|
$var wire 1 WN reqq_req_st0 $end
|
|
$var wire 42 /X! reqq_req_tag_st0 [41:0] $end
|
|
$var wire 2 _N reqq_req_tid_st0 [1:0] $end
|
|
$var wire 32 !O reqq_req_writedata_st0 [31:0] $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 1 gh! use_empty $end
|
|
$var wire 120 }g! use_per_addr [119:0] $end
|
|
$var wire 16 ug! use_per_byteen [15:0] $end
|
|
$var wire 4 mg! use_per_rw [3:0] $end
|
|
$var wire 42 /X! use_per_tag [41:0] $end
|
|
$var wire 4 eg! use_per_valids [3:0] $end
|
|
$var wire 128 ?h! use_per_writedata [127:0] $end
|
|
$scope module reqq_queue $end
|
|
$var wire 32 wn" BUFFERED_OUTPUT [31:0] $end
|
|
$var wire 32 yo" DATAW [31:0] $end
|
|
$var wire 32 on" SIZE [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 314 {$ data_in [313:0] $end
|
|
$var wire 314 CX data_out [313:0] $end
|
|
$var wire 1 _h! empty $end
|
|
$var wire 1 'X! full $end
|
|
$var wire 1 3X pop $end
|
|
$var wire 1 o* push $end
|
|
$var wire 1 5Y reading $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 3 oh! size [2:0] $end
|
|
$var wire 3 oh! size_r [2:0] $end
|
|
$var wire 1 m% writing $end
|
|
$scope module genblk3 $end
|
|
$var wire 314 wh! data(0) [313:0] $end
|
|
$var wire 314 #i! data(1) [313:0] $end
|
|
$var wire 314 -i! data(2) [313:0] $end
|
|
$var wire 314 7i! data(3) [313:0] $end
|
|
$scope module genblk2 $end
|
|
$var wire 1 ;n! bypass_r $end
|
|
$var wire 314 1m! curr_r [313:0] $end
|
|
$var wire 1 _h! empty_r $end
|
|
$var wire 1 'X! full_r $end
|
|
$var wire 314 ?l! head_r [313:0] $end
|
|
$var wire 2 3n! rd_ptr_next_r [1:0] $end
|
|
$var wire 2 +n! rd_ptr_r [1:0] $end
|
|
$var wire 2 #n! wr_ptr_r [1:0] $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope module sel_bank $end
|
|
$var wire 32 on" N [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 2 _N grant_index [1:0] $end
|
|
$var wire 4 =Y grant_onehot [3:0] $end
|
|
$var wire 1 WN grant_valid $end
|
|
$var wire 4 eg! requests [3:0] $end
|
|
$var wire 1 [h" reset $end
|
|
$scope module genblk2 $end
|
|
$var wire 4 =Y grant_onehot_r [3:0] $end
|
|
$scope module priority_encoder $end
|
|
$var wire 32 on" N [31:0] $end
|
|
$var wire 4 eg! data_in [3:0] $end
|
|
$var wire 2 _N data_out [1:0] $end
|
|
$var wire 32 EY i [31:0] $end
|
|
$var wire 1 WN valid_out $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope module cwb_queue $end
|
|
$var wire 32 wn" BUFFERED_OUTPUT [31:0] $end
|
|
$var wire 32 ;p" DATAW [31:0] $end
|
|
$var wire 32 on" SIZE [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 76 3` data_in [75:0] $end
|
|
$var wire 76 K` data_out [75:0] $end
|
|
$var wire 1 U[! empty $end
|
|
$var wire 1 ][! full $end
|
|
$var wire 1 _* pop $end
|
|
$var wire 1 MU push $end
|
|
$var wire 1 u% reading $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 3 cv! size [2:0] $end
|
|
$var wire 3 cv! size_r [2:0] $end
|
|
$var wire 1 c` writing $end
|
|
$scope module genblk3 $end
|
|
$var wire 76 kv! data(0) [75:0] $end
|
|
$var wire 76 nv! data(1) [75:0] $end
|
|
$var wire 76 qv! data(2) [75:0] $end
|
|
$var wire 76 tv! data(3) [75:0] $end
|
|
$scope module genblk2 $end
|
|
$var wire 1 Wx! bypass_r $end
|
|
$var wire 76 'x! curr_r [75:0] $end
|
|
$var wire 1 U[! empty_r $end
|
|
$var wire 1 ][! full_r $end
|
|
$var wire 76 mw! head_r [75:0] $end
|
|
$var wire 2 Ox! rd_ptr_next_r [1:0] $end
|
|
$var wire 2 Gx! rd_ptr_r [1:0] $end
|
|
$var wire 2 ?x! wr_ptr_r [1:0] $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope module dfp_queue $end
|
|
$var wire 32 wn" BUFFERED_OUTPUT [31:0] $end
|
|
$var wire 32 qo" DATAW [31:0] $end
|
|
$var wire 32 gn" SIZE [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 154 K$ data_in [153:0] $end
|
|
$var wire 154 OV data_out [153:0] $end
|
|
$var wire 1 uW! empty $end
|
|
$var wire 1 }W! full $end
|
|
$var wire 1 uM pop $end
|
|
$var wire 1 um" push $end
|
|
$var wire 1 wV reading $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 5 ]_! size [4:0] $end
|
|
$var wire 5 ]_! size_r [4:0] $end
|
|
$var wire 1 s$ writing $end
|
|
$scope module genblk3 $end
|
|
$var wire 154 e_! data(0) [153:0] $end
|
|
$var wire 154 j_! data(1) [153:0] $end
|
|
$var wire 154 9`! data(10) [153:0] $end
|
|
$var wire 154 >`! data(11) [153:0] $end
|
|
$var wire 154 C`! data(12) [153:0] $end
|
|
$var wire 154 H`! data(13) [153:0] $end
|
|
$var wire 154 M`! data(14) [153:0] $end
|
|
$var wire 154 R`! data(15) [153:0] $end
|
|
$var wire 154 o_! data(2) [153:0] $end
|
|
$var wire 154 t_! data(3) [153:0] $end
|
|
$var wire 154 y_! data(4) [153:0] $end
|
|
$var wire 154 ~_! data(5) [153:0] $end
|
|
$var wire 154 %`! data(6) [153:0] $end
|
|
$var wire 154 *`! data(7) [153:0] $end
|
|
$var wire 154 /`! data(8) [153:0] $end
|
|
$var wire 154 4`! data(9) [153:0] $end
|
|
$scope module genblk2 $end
|
|
$var wire 1 ]g! bypass_r $end
|
|
$var wire 154 {f! curr_r [153:0] $end
|
|
$var wire 1 uW! empty_r $end
|
|
$var wire 1 }W! full_r $end
|
|
$var wire 154 Sf! head_r [153:0] $end
|
|
$var wire 4 Ug! rd_ptr_next_r [3:0] $end
|
|
$var wire 4 Mg! rd_ptr_r [3:0] $end
|
|
$var wire 4 Eg! wr_ptr_r [3:0] $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope module dwb_queue $end
|
|
$var wire 32 wn" BUFFERED_OUTPUT [31:0] $end
|
|
$var wire 32 Cp" DATAW [31:0] $end
|
|
$var wire 32 on" SIZE [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 200 k` data_in [199:0] $end
|
|
$var wire 200 Ea data_out [199:0] $end
|
|
$var wire 1 e[! empty $end
|
|
$var wire 1 m[! full $end
|
|
$var wire 1 g* pop $end
|
|
$var wire 1 eU push $end
|
|
$var wire 1 }% reading $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 3 _x! size [2:0] $end
|
|
$var wire 3 _x! size_r [2:0] $end
|
|
$var wire 1 }a writing $end
|
|
$scope module genblk3 $end
|
|
$var wire 200 gx! data(0) [199:0] $end
|
|
$var wire 200 nx! data(1) [199:0] $end
|
|
$var wire 200 ux! data(2) [199:0] $end
|
|
$var wire 200 |x! data(3) [199:0] $end
|
|
$scope module genblk2 $end
|
|
$var wire 1 W|! bypass_r $end
|
|
$var wire 200 e{! curr_r [199:0] $end
|
|
$var wire 1 e[! empty_r $end
|
|
$var wire 1 m[! full_r $end
|
|
$var wire 200 -{! head_r [199:0] $end
|
|
$var wire 2 O|! rd_ptr_next_r [1:0] $end
|
|
$var wire 2 G|! rd_ptr_r [1:0] $end
|
|
$var wire 2 ?|! wr_ptr_r [1:0] $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope module s0_1_c0 $end
|
|
$var wire 32 #p" N [31:0] $end
|
|
$var wire 32 Wn" PASSTHRU [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 1 Io" flush $end
|
|
$var wire 243 MY in [242:0] $end
|
|
$var wire 243 Cn! out [242:0] $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 1 #P stall $end
|
|
$var wire 243 Cn! value [242:0] $end
|
|
$upscope $end
|
|
$scope module snp_req_queue $end
|
|
$var wire 32 wn" BUFFERED_OUTPUT [31:0] $end
|
|
$var wire 32 io" DATAW [31:0] $end
|
|
$var wire 32 gn" SIZE [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 55 3$ data_in [54:0] $end
|
|
$var wire 55 7V data_out [54:0] $end
|
|
$var wire 1 eW! empty $end
|
|
$var wire 1 mW! full $end
|
|
$var wire 1 UM pop $end
|
|
$var wire 1 }m" push $end
|
|
$var wire 1 GV reading $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 5 /\! size [4:0] $end
|
|
$var wire 5 /\! size_r [4:0] $end
|
|
$var wire 1 C$ writing $end
|
|
$scope module genblk3 $end
|
|
$var wire 55 7\! data(0) [54:0] $end
|
|
$var wire 55 9\! data(1) [54:0] $end
|
|
$var wire 55 K\! data(10) [54:0] $end
|
|
$var wire 55 M\! data(11) [54:0] $end
|
|
$var wire 55 O\! data(12) [54:0] $end
|
|
$var wire 55 Q\! data(13) [54:0] $end
|
|
$var wire 55 S\! data(14) [54:0] $end
|
|
$var wire 55 U\! data(15) [54:0] $end
|
|
$var wire 55 ;\! data(2) [54:0] $end
|
|
$var wire 55 =\! data(3) [54:0] $end
|
|
$var wire 55 ?\! data(4) [54:0] $end
|
|
$var wire 55 A\! data(5) [54:0] $end
|
|
$var wire 55 C\! data(6) [54:0] $end
|
|
$var wire 55 E\! data(7) [54:0] $end
|
|
$var wire 55 G\! data(8) [54:0] $end
|
|
$var wire 55 I\! data(9) [54:0] $end
|
|
$scope module genblk2 $end
|
|
$var wire 1 U_! bypass_r $end
|
|
$var wire 55 -_! curr_r [54:0] $end
|
|
$var wire 1 eW! empty_r $end
|
|
$var wire 1 mW! full_r $end
|
|
$var wire 55 {^! head_r [54:0] $end
|
|
$var wire 4 M_! rd_ptr_next_r [3:0] $end
|
|
$var wire 4 E_! rd_ptr_r [3:0] $end
|
|
$var wire 4 =_! wr_ptr_r [3:0] $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope module st_1e_2 $end
|
|
$var wire 32 3p" N [31:0] $end
|
|
$var wire 32 Wn" PASSTHRU [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 1 Io" flush $end
|
|
$var wire 316 W^ in [315:0] $end
|
|
$var wire 316 'p! out [315:0] $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 1 #P stall $end
|
|
$var wire 316 'p! value [315:0] $end
|
|
$upscope $end
|
|
$scope module tag_data_access $end
|
|
$var wire 32 gn" BANK_LINE_SIZE [31:0] $end
|
|
$var wire 32 _n" CACHE_SIZE [31:0] $end
|
|
$var wire 32 wn" DRAM_ENABLE [31:0] $end
|
|
$var wire 32 on" NUM_BANKS [31:0] $end
|
|
$var wire 32 wn" STAGE_1_CYCLES [31:0] $end
|
|
$var wire 32 on" WORD_SIZE [31:0] $end
|
|
$var wire 32 wn" WRITE_ENABLE [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 128 K\ data_write [127:0] $end
|
|
$var wire 1 IS dirty_st1e $end
|
|
$var wire 16 QS dirtyb_st1e [15:0] $end
|
|
$var wire 1 #T fill_saw_dirty_st1e $end
|
|
$var wire 1 AS fill_sent $end
|
|
$var wire 1 U] force_core_miss $end
|
|
$var wire 1 QO force_request_miss_st1e $end
|
|
$var wire 1 k\ invalidate_line $end
|
|
$var wire 1 +T is_snp_st1e $end
|
|
$var wire 4 yS mem_byteen_st1e [3:0] $end
|
|
$var wire 1 qS mem_rw_st1e $end
|
|
$var wire 1 AS miss_st1e $end
|
|
$var wire 1 CT mrvq_init_ready_state_st1e $end
|
|
$var wire 128 q[ qual_read_data_st1 [127:0] $end
|
|
$var wire 1 Y[ qual_read_dirty_st1 $end
|
|
$var wire 16 a[ qual_read_dirtyb_st1 [15:0] $end
|
|
$var wire 20 i[ qual_read_tag_st1 [19:0] $end
|
|
$var wire 1 Q[ qual_read_valid_st1 $end
|
|
$var wire 128 1[ read_data_st1c(0) [127:0] $end
|
|
$var wire 1 wZ read_dirty_st1c(0) $end
|
|
$var wire 16 ![ read_dirtyb_st1c(0) [15:0] $end
|
|
$var wire 20 )[ read_tag_st1c(0) [19:0] $end
|
|
$var wire 1 oZ read_valid_st1c(0) $end
|
|
$var wire 6 /Z readaddr_st10 [5:0] $end
|
|
$var wire 128 wR readdata_st1e [127:0] $end
|
|
$var wire 20 9S readtag_st1e [19:0] $end
|
|
$var wire 32 oR readword_st1e [31:0] $end
|
|
$var wire 1 M] real_miss $end
|
|
$var wire 1 {\ real_writefill $end
|
|
$var wire 1 =] req_invalid $end
|
|
$var wire 1 E] req_miss $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 1 5] should_write $end
|
|
$var wire 1 k\ snoop_hit_no_pending $end
|
|
$var wire 1 3T snp_invalidate_st1e $end
|
|
$var wire 1 ;T snp_to_mrvq_st1e $end
|
|
$var wire 1 #P stall $end
|
|
$var wire 1 #P stall_bank_pipe $end
|
|
$var wire 1 s\ tags_match $end
|
|
$var wire 128 wR use_read_data_st1e [127:0] $end
|
|
$var wire 1 ;\ use_read_dirty_st1e $end
|
|
$var wire 16 QS use_read_dirtyb_st1e [15:0] $end
|
|
$var wire 20 9S use_read_tag_st1e [19:0] $end
|
|
$var wire 1 3\ use_read_valid_st1e $end
|
|
$var wire 128 K\ use_write_data [127:0] $end
|
|
$var wire 16 C\ use_write_enable [15:0] $end
|
|
$var wire 1 ST valid_req_st1e $end
|
|
$var wire 16 -] we [15:0] $end
|
|
$var wire 2 gZ wordsel_st1e [1:0] $end
|
|
$var wire 26 kT writeaddr_st1e [25:0] $end
|
|
$var wire 128 GZ writedata_st1e [127:0] $end
|
|
$var wire 1 7Z writefill_st1e $end
|
|
$var wire 6 /Z writeladdr_st1e [5:0] $end
|
|
$var wire 20 %] writetag_st1e [19:0] $end
|
|
$var wire 32 ?Z writeword_st1e [31:0] $end
|
|
$scope module genblk4(0) $end
|
|
$var wire 1 ]] normal_write $end
|
|
$upscope $end
|
|
$scope module genblk4(1) $end
|
|
$var wire 1 e] normal_write $end
|
|
$upscope $end
|
|
$scope module genblk4(2) $end
|
|
$var wire 1 m] normal_write $end
|
|
$upscope $end
|
|
$scope module genblk4(3) $end
|
|
$var wire 1 u] normal_write $end
|
|
$upscope $end
|
|
$scope module s0_1_c0 $end
|
|
$var wire 32 +p" N [31:0] $end
|
|
$var wire 32 wn" PASSTHRU [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 1 Io" flush $end
|
|
$var wire 166 '^ in [165:0] $end
|
|
$var wire 166 '^ out [165:0] $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 1 #P stall $end
|
|
$var wire 166 Uo! value [165:0] $end
|
|
$upscope $end
|
|
$scope module tag_data_structure $end
|
|
$var wire 32 gn" BANK_LINE_SIZE [31:0] $end
|
|
$var wire 32 _n" CACHE_SIZE [31:0] $end
|
|
$var wire 32 on" NUM_BANKS [31:0] $end
|
|
$var wire 32 on" WORD_SIZE [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 64 %o! dirty [63:0] $end
|
|
$var wire 1 }] do_write $end
|
|
$var wire 1 AS fill_sent $end
|
|
$var wire 32 Eo! i [31:0] $end
|
|
$var wire 1 k\ invalidate $end
|
|
$var wire 32 Mo! j [31:0] $end
|
|
$var wire 6 /Z read_addr [5:0] $end
|
|
$var wire 128 q[ read_data [127:0] $end
|
|
$var wire 1 Y[ read_dirty $end
|
|
$var wire 16 a[ read_dirtyb [15:0] $end
|
|
$var wire 20 i[ read_tag [19:0] $end
|
|
$var wire 1 Q[ read_valid $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 1 #P stall_bank_pipe $end
|
|
$var wire 20 %] tag_index [19:0] $end
|
|
$var wire 64 5o! valid [63:0] $end
|
|
$var wire 6 /Z write_addr [5:0] $end
|
|
$var wire 128 K\ write_data [127:0] $end
|
|
$var wire 16 C\ write_enable [15:0] $end
|
|
$var wire 1 {\ write_fill $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope module genblk5(2) $end
|
|
$var wire 120 {h" curr_bank_core_req_addr [119:0] $end
|
|
$var wire 16 sh" curr_bank_core_req_byteen [15:0] $end
|
|
$var wire 128 =i" curr_bank_core_req_data [127:0] $end
|
|
$var wire 1 C.! curr_bank_core_req_ready $end
|
|
$var wire 4 kh" curr_bank_core_req_rw [3:0] $end
|
|
$var wire 42 ]i" curr_bank_core_req_tag [41:0] $end
|
|
$var wire 4 %! curr_bank_core_req_valid [3:0] $end
|
|
$var wire 32 /2 curr_bank_core_rsp_data [31:0] $end
|
|
$var wire 1 -! curr_bank_core_rsp_ready $end
|
|
$var wire 42 72 curr_bank_core_rsp_tag [41:0] $end
|
|
$var wire 2 '2 curr_bank_core_rsp_tid [1:0] $end
|
|
$var wire 1 #.! curr_bank_core_rsp_valid $end
|
|
$var wire 26 3.! curr_bank_dram_fill_req_addr [25:0] $end
|
|
$var wire 1 )-! curr_bank_dram_fill_req_ready $end
|
|
$var wire 1 G2 curr_bank_dram_fill_req_valid $end
|
|
$var wire 26 ]m" curr_bank_dram_fill_rsp_addr [25:0] $end
|
|
$var wire 128 Qk" curr_bank_dram_fill_rsp_data [127:0] $end
|
|
$var wire 1 +.! curr_bank_dram_fill_rsp_ready $end
|
|
$var wire 1 'n" curr_bank_dram_fill_rsp_valid $end
|
|
$var wire 26 _2 curr_bank_dram_wb_req_addr [25:0] $end
|
|
$var wire 16 W2 curr_bank_dram_wb_req_byteen [15:0] $end
|
|
$var wire 128 g2 curr_bank_dram_wb_req_data [127:0] $end
|
|
$var wire 1 5! curr_bank_dram_wb_req_ready $end
|
|
$var wire 1 O2 curr_bank_dram_wb_req_valid $end
|
|
$var wire 26 mm" curr_bank_snp_req_addr [25:0] $end
|
|
$var wire 1 3l" curr_bank_snp_req_invalidate $end
|
|
$var wire 1 ;.! curr_bank_snp_req_ready $end
|
|
$var wire 28 ;l" curr_bank_snp_req_tag [27:0] $end
|
|
$var wire 1 /n" curr_bank_snp_req_valid $end
|
|
$var wire 1 =! curr_bank_snp_rsp_ready $end
|
|
$var wire 28 13 curr_bank_snp_rsp_tag [27:0] $end
|
|
$var wire 1 )3 curr_bank_snp_rsp_valid $end
|
|
$scope module bank $end
|
|
$var wire 32 Kp" BANK_ID [31:0] $end
|
|
$var wire 32 gn" BANK_LINE_SIZE [31:0] $end
|
|
$var wire 32 Wn" CACHE_ID [31:0] $end
|
|
$var wire 32 _n" CACHE_SIZE [31:0] $end
|
|
$var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end
|
|
$var wire 32 !o" CORE_TAG_WIDTH [31:0] $end
|
|
$var wire 32 on" CREQ_SIZE [31:0] $end
|
|
$var wire 32 on" CWBQ_SIZE [31:0] $end
|
|
$var wire 32 gn" DFPQ_SIZE [31:0] $end
|
|
$var wire 32 on" DFQQ_SIZE [31:0] $end
|
|
$var wire 32 wn" DRAM_ENABLE [31:0] $end
|
|
$var wire 32 on" DWBQ_SIZE [31:0] $end
|
|
$var wire 32 gn" MRVQ_SIZE [31:0] $end
|
|
$var wire 32 on" NUM_BANKS [31:0] $end
|
|
$var wire 32 on" NUM_REQUESTS [31:0] $end
|
|
$var wire 32 Wn" SNOOP_FORWARDING [31:0] $end
|
|
$var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end
|
|
$var wire 32 gn" SNRQ_SIZE [31:0] $end
|
|
$var wire 32 wn" STAGE_1_CYCLES [31:0] $end
|
|
$var wire 32 on" WORD_SIZE [31:0] $end
|
|
$var wire 32 wn" WRITE_ENABLE [31:0] $end
|
|
$var wire 26 ?f addr_st1(0) [25:0] $end
|
|
$var wire 26 =i addr_st1e [25:0] $end
|
|
$var wire 26 3.! addr_st2 [25:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 120 {h" core_req_addr [119:0] $end
|
|
$var wire 16 sh" core_req_byteen [15:0] $end
|
|
$var wire 128 =i" core_req_data [127:0] $end
|
|
$var wire 1 C.! core_req_ready $end
|
|
$var wire 4 kh" core_req_rw [3:0] $end
|
|
$var wire 42 ]i" core_req_tag [41:0] $end
|
|
$var wire 4 %! core_req_valid [3:0] $end
|
|
$var wire 32 /2 core_rsp_data [31:0] $end
|
|
$var wire 1 -! core_rsp_ready $end
|
|
$var wire 42 72 core_rsp_tag [41:0] $end
|
|
$var wire 2 '2 core_rsp_tid [1:0] $end
|
|
$var wire 1 #.! core_rsp_valid $end
|
|
$var wire 32 {~! cwbq_data [31:0] $end
|
|
$var wire 1 O"" cwbq_empty $end
|
|
$var wire 1 W"" cwbq_full $end
|
|
$var wire 1 !+ cwbq_pop $end
|
|
$var wire 1 }i cwbq_push $end
|
|
$var wire 1 ;d cwbq_push_stall $end
|
|
$var wire 1 'j cwbq_push_unqual $end
|
|
$var wire 42 ;~! cwbq_tag [41:0] $end
|
|
$var wire 2 3~! cwbq_tid [1:0] $end
|
|
$var wire 26 Ob dfpq_addr_st0 [25:0] $end
|
|
$var wire 1 o|! dfpq_empty $end
|
|
$var wire 128 Wb dfpq_filldata_st0 [127:0] $end
|
|
$var wire 1 w|! dfpq_full $end
|
|
$var wire 1 Gb dfpq_pop $end
|
|
$var wire 1 sd dfpq_pop_unqual $end
|
|
$var wire 1 yg dirty_st1e $end
|
|
$var wire 1 M!" dirty_st2 $end
|
|
$var wire 16 #h dirtyb_st1e [15:0] $end
|
|
$var wire 16 U!" dirtyb_st2 [15:0] $end
|
|
$var wire 26 3.! dram_fill_req_addr [25:0] $end
|
|
$var wire 1 ei dram_fill_req_fast $end
|
|
$var wire 1 )-! dram_fill_req_ready $end
|
|
$var wire 1 Kd dram_fill_req_stall $end
|
|
$var wire 1 /j dram_fill_req_unqual $end
|
|
$var wire 1 G2 dram_fill_req_valid $end
|
|
$var wire 26 ]m" dram_fill_rsp_addr [25:0] $end
|
|
$var wire 128 Qk" dram_fill_rsp_data [127:0] $end
|
|
$var wire 1 +.! dram_fill_rsp_ready $end
|
|
$var wire 1 'n" dram_fill_rsp_valid $end
|
|
$var wire 26 _2 dram_wb_req_addr [25:0] $end
|
|
$var wire 16 W2 dram_wb_req_byteen [15:0] $end
|
|
$var wire 128 g2 dram_wb_req_data [127:0] $end
|
|
$var wire 1 '& dram_wb_req_fire $end
|
|
$var wire 1 5! dram_wb_req_ready $end
|
|
$var wire 1 O2 dram_wb_req_valid $end
|
|
$var wire 1 !#" dwbq_dual_valid_sel $end
|
|
$var wire 1 _"" dwbq_empty $end
|
|
$var wire 1 g"" dwbq_full $end
|
|
$var wire 1 ?j dwbq_is_dwb_in $end
|
|
$var wire 1 Oj dwbq_is_dwb_out $end
|
|
$var wire 1 Gj dwbq_is_snp_in $end
|
|
$var wire 1 Wj dwbq_is_snp_out $end
|
|
$var wire 1 )+ dwbq_pop $end
|
|
$var wire 1 7j dwbq_push $end
|
|
$var wire 1 Cd dwbq_push_stall $end
|
|
$var wire 1 _j dwbq_push_unqual $end
|
|
$var wire 26 o"" dwbq_req_addr [25:0] $end
|
|
$var wire 1 Sh fill_saw_dirty_st1e $end
|
|
$var wire 1 u!" fill_saw_dirty_st2 $end
|
|
$var wire 1 #d force_request_miss_st1e $end
|
|
$var wire 1 kd going_to_write_st1(0) $end
|
|
$var wire 49 Wf inst_meta_st1(0) [48:0] $end
|
|
$var wire 49 ]!" inst_meta_st2 [48:0] $end
|
|
$var wire 1 [d is_fill_in_pipe $end
|
|
$var wire 1 cd is_fill_st1(0) $end
|
|
$var wire 1 [~! is_fill_st2 $end
|
|
$var wire 1 9g is_mrvq_st1(0) $end
|
|
$var wire 1 -i is_mrvq_st1e $end
|
|
$var wire 1 -i is_mrvq_st1e_st2 $end
|
|
$var wire 1 7"" is_mrvq_st2 $end
|
|
$var wire 1 )g is_snp_st1(0) $end
|
|
$var wire 1 [h is_snp_st1e $end
|
|
$var wire 1 }!" is_snp_st2 $end
|
|
$var wire 32 ao" j [31:0] $end
|
|
$var wire 4 Kh mem_byteen_st1e [3:0] $end
|
|
$var wire 1 Ch mem_rw_st1e $end
|
|
$var wire 1 mi miss_add $end
|
|
$var wire 26 3.! miss_add_addr [25:0] $end
|
|
$var wire 1 {h miss_add_because_miss $end
|
|
$var wire 1 /"" miss_add_because_pending $end
|
|
$var wire 4 S~! miss_add_byteen [3:0] $end
|
|
$var wire 32 s~! miss_add_data [31:0] $end
|
|
$var wire 1 ui miss_add_is_mrvq $end
|
|
$var wire 1 }!" miss_add_is_snp $end
|
|
$var wire 1 K~! miss_add_rw $end
|
|
$var wire 1 '"" miss_add_snp_invalidate $end
|
|
$var wire 42 ;~! miss_add_tag [41:0] $end
|
|
$var wire 2 3~! miss_add_tid [1:0] $end
|
|
$var wire 1 ei miss_add_unqual $end
|
|
$var wire 2 k~! miss_add_wsel [1:0] $end
|
|
$var wire 1 qg miss_st1e $end
|
|
$var wire 1 E!" miss_st2 $end
|
|
$var wire 26 Q}! mrvq_addr_st0 [25:0] $end
|
|
$var wire 4 y}! mrvq_byteen_st0 [3:0] $end
|
|
$var wire 1 9}! mrvq_full $end
|
|
$var wire 1 Ui mrvq_init_ready_state_hazard_st0_st1 $end
|
|
$var wire 1 ]i mrvq_init_ready_state_hazard_st1e_st1 $end
|
|
$var wire 1 sh mrvq_init_ready_state_st1e $end
|
|
$var wire 1 Mi mrvq_init_ready_state_st2 $end
|
|
$var wire 1 G"" mrvq_init_ready_state_unqual_st2 $end
|
|
$var wire 1 #~! mrvq_is_snp_st0 $end
|
|
$var wire 1 qc mrvq_pending_hazard_st1e $end
|
|
$var wire 1 Yc mrvq_pop $end
|
|
$var wire 1 ac mrvq_pop_unqual $end
|
|
$var wire 1 3d mrvq_push_stall $end
|
|
$var wire 1 5i mrvq_recover_ready_state_st1e $end
|
|
$var wire 1 ?"" mrvq_recover_ready_state_st2 $end
|
|
$var wire 1 ic mrvq_rw_st0 $end
|
|
$var wire 1 +~! mrvq_snp_invalidate_st0 $end
|
|
$var wire 1 A}! mrvq_stop $end
|
|
$var wire 42 i}! mrvq_tag_st0 [41:0] $end
|
|
$var wire 2 I}! mrvq_tid_st0 [1:0] $end
|
|
$var wire 1 ac mrvq_valid_st0 $end
|
|
$var wire 32 a}! mrvq_writeword_st0 [31:0] $end
|
|
$var wire 2 Y}! mrvq_wsel_st0 [1:0] $end
|
|
$var wire 26 5e qual_addr_st0 [25:0] $end
|
|
$var wire 1 }e qual_going_to_write_st0 $end
|
|
$var wire 49 me qual_inst_meta_st0 [48:0] $end
|
|
$var wire 1 sd qual_is_fill_st0 $end
|
|
$var wire 1 ac qual_is_mrvq_st0 $end
|
|
$var wire 1 'f qual_is_snp_st0 $end
|
|
$var wire 1 /f qual_snp_invalidate_st0 $end
|
|
$var wire 1 -e qual_valid_st0 $end
|
|
$var wire 1 Ei qual_valid_st1e_2 $end
|
|
$var wire 128 Me qual_writedata_st0 [127:0] $end
|
|
$var wire 32 Ee qual_writeword_st0 [31:0] $end
|
|
$var wire 2 =e qual_wsel_st0 [1:0] $end
|
|
$var wire 128 Ig readdata_st1e [127:0] $end
|
|
$var wire 128 %!" readdata_st2 [127:0] $end
|
|
$var wire 20 ig readtag_st1e [19:0] $end
|
|
$var wire 20 m!" readtag_st2 [19:0] $end
|
|
$var wire 32 Ag readword_st1e [31:0] $end
|
|
$var wire 32 {~! readword_st2 [31:0] $end
|
|
$var wire 1 +d recover_mrvq_state_st2 $end
|
|
$var wire 1 !c reqq_empty $end
|
|
$var wire 1 !}! reqq_full $end
|
|
$var wire 1 wb reqq_pop $end
|
|
$var wire 1 {d reqq_pop_unqual $end
|
|
$var wire 1 w* reqq_push $end
|
|
$var wire 30 Ic reqq_req_addr_st0 [29:0] $end
|
|
$var wire 4 Ac reqq_req_byteen_st0 [3:0] $end
|
|
$var wire 1 9c reqq_req_rw_st0 $end
|
|
$var wire 1 )c reqq_req_st0 $end
|
|
$var wire 42 )}! reqq_req_tag_st0 [41:0] $end
|
|
$var wire 2 1c reqq_req_tid_st0 [1:0] $end
|
|
$var wire 32 Qc reqq_req_writeword_st0 [31:0] $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 1 1g snp_invalidate_st1(0) $end
|
|
$var wire 1 ch snp_invalidate_st1e $end
|
|
$var wire 1 '"" snp_invalidate_st2 $end
|
|
$var wire 26 mm" snp_req_addr [25:0] $end
|
|
$var wire 1 3l" snp_req_invalidate $end
|
|
$var wire 1 ;.! snp_req_ready $end
|
|
$var wire 28 ;l" snp_req_tag [27:0] $end
|
|
$var wire 1 /n" snp_req_valid $end
|
|
$var wire 1 /& snp_rsp_fire $end
|
|
$var wire 1 =! snp_rsp_ready $end
|
|
$var wire 28 13 snp_rsp_tag [27:0] $end
|
|
$var wire 1 )3 snp_rsp_valid $end
|
|
$var wire 1 kh snp_to_mrvq_st1e $end
|
|
$var wire 1 /"" snp_to_mrvq_st2 $end
|
|
$var wire 26 /b snrq_addr_st0 [25:0] $end
|
|
$var wire 1 _|! snrq_empty $end
|
|
$var wire 1 g|! snrq_full $end
|
|
$var wire 1 7b snrq_invalidate_st0 $end
|
|
$var wire 1 'b snrq_pop $end
|
|
$var wire 1 %e snrq_pop_unqual $end
|
|
$var wire 28 ?b snrq_tag_st0 [27:0] $end
|
|
$var wire 28 w"" snrq_tag_st2 [27:0] $end
|
|
$var wire 1 yc st2_pending_hazard_st1e $end
|
|
$var wire 1 Sd stall_bank_pipe $end
|
|
$var wire 42 +h tag_st1e [41:0] $end
|
|
$var wire 2 ;h tid_st1e [1:0] $end
|
|
$var wire 1 7f valid_st1(0) $end
|
|
$var wire 1 %i valid_st1e $end
|
|
$var wire 1 c~! valid_st2 $end
|
|
$var wire 128 gf writedata_st1(0) [127:0] $end
|
|
$var wire 32 Of writeword_st1(0) [31:0] $end
|
|
$var wire 32 s~! writeword_st2 [31:0] $end
|
|
$var wire 2 Gf wsel_st1(0) [1:0] $end
|
|
$var wire 2 k~! wsel_st2 [1:0] $end
|
|
$scope module cache_miss_resrv $end
|
|
$var wire 32 Kp" BANK_ID [31:0] $end
|
|
$var wire 32 gn" BANK_LINE_SIZE [31:0] $end
|
|
$var wire 32 Wn" CACHE_ID [31:0] $end
|
|
$var wire 32 !o" CORE_TAG_WIDTH [31:0] $end
|
|
$var wire 32 gn" MRVQ_SIZE [31:0] $end
|
|
$var wire 32 on" NUM_BANKS [31:0] $end
|
|
$var wire 32 on" NUM_REQUESTS [31:0] $end
|
|
$var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end
|
|
$var wire 32 on" WORD_SIZE [31:0] $end
|
|
$var wire 416 y;" addr_table [415:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 4 5=" dequeue_index [3:0] $end
|
|
$var wire 1 ac dequeue_possible $end
|
|
$var wire 4 E=" enqueue_index [3:0] $end
|
|
$var wire 1 U=" enqueue_possible $end
|
|
$var wire 26 =i fill_addr_st1 [25:0] $end
|
|
$var wire 4 ==" head_ptr [3:0] $end
|
|
$var wire 1 Kt increment_head $end
|
|
$var wire 1 gn is_fill_st1 $end
|
|
$var wire 1 ui is_mrvq $end
|
|
$var wire 16 ys make_ready [15:0] $end
|
|
$var wire 16 #t make_ready_push [15:0] $end
|
|
$var wire 85 q7" metadata_table(0) [84:0] $end
|
|
$var wire 85 t7" metadata_table(1) [84:0] $end
|
|
$var wire 85 18" metadata_table(10) [84:0] $end
|
|
$var wire 85 48" metadata_table(11) [84:0] $end
|
|
$var wire 85 78" metadata_table(12) [84:0] $end
|
|
$var wire 85 :8" metadata_table(13) [84:0] $end
|
|
$var wire 85 =8" metadata_table(14) [84:0] $end
|
|
$var wire 85 @8" metadata_table(15) [84:0] $end
|
|
$var wire 85 w7" metadata_table(2) [84:0] $end
|
|
$var wire 85 z7" metadata_table(3) [84:0] $end
|
|
$var wire 85 }7" metadata_table(4) [84:0] $end
|
|
$var wire 85 "8" metadata_table(5) [84:0] $end
|
|
$var wire 85 %8" metadata_table(6) [84:0] $end
|
|
$var wire 85 (8" metadata_table(7) [84:0] $end
|
|
$var wire 85 +8" metadata_table(8) [84:0] $end
|
|
$var wire 85 .8" metadata_table(9) [84:0] $end
|
|
$var wire 1 mi miss_add $end
|
|
$var wire 26 3.! miss_add_addr [25:0] $end
|
|
$var wire 4 S~! miss_add_byteen [3:0] $end
|
|
$var wire 32 s~! miss_add_data [31:0] $end
|
|
$var wire 1 }!" miss_add_is_snp $end
|
|
$var wire 1 K~! miss_add_rw $end
|
|
$var wire 1 '"" miss_add_snp_invalidate $end
|
|
$var wire 42 ;~! miss_add_tag [41:0] $end
|
|
$var wire 2 3~! miss_add_tid [1:0] $end
|
|
$var wire 2 k~! miss_add_wsel [1:0] $end
|
|
$var wire 26 Q}! miss_resrv_addr_st0 [25:0] $end
|
|
$var wire 4 y}! miss_resrv_byteen_st0 [3:0] $end
|
|
$var wire 32 a}! miss_resrv_data_st0 [31:0] $end
|
|
$var wire 1 9}! miss_resrv_full $end
|
|
$var wire 1 #~! miss_resrv_is_snp_st0 $end
|
|
$var wire 1 Yc miss_resrv_pop $end
|
|
$var wire 1 ic miss_resrv_rw_st0 $end
|
|
$var wire 1 +~! miss_resrv_snp_invalidate_st0 $end
|
|
$var wire 1 A}! miss_resrv_stop $end
|
|
$var wire 42 i}! miss_resrv_tag_st0 [41:0] $end
|
|
$var wire 2 I}! miss_resrv_tid_st0 [1:0] $end
|
|
$var wire 1 ac miss_resrv_valid_st0 $end
|
|
$var wire 2 Y}! miss_resrv_wsel_st0 [1:0] $end
|
|
$var wire 1 Mi mrvq_init_ready_state $end
|
|
$var wire 1 ;t mrvq_pop $end
|
|
$var wire 1 3t mrvq_push $end
|
|
$var wire 1 qc pending_hazard $end
|
|
$var wire 1 [t qual_mrvq_init $end
|
|
$var wire 16 -=" ready_table [15:0] $end
|
|
$var wire 1 Ct recover_state $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 4 5=" schedule_ptr [3:0] $end
|
|
$var wire 5 M=" size [4:0] $end
|
|
$var wire 4 E=" tail_ptr [3:0] $end
|
|
$var wire 1 St update_ready $end
|
|
$var wire 16 +t valid_address_match [15:0] $end
|
|
$var wire 16 %=" valid_table [15:0] $end
|
|
$upscope $end
|
|
$scope module core_req_arb $end
|
|
$var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end
|
|
$var wire 32 !o" CORE_TAG_WIDTH [31:0] $end
|
|
$var wire 32 on" CREQ_SIZE [31:0] $end
|
|
$var wire 32 on" NUM_REQUESTS [31:0] $end
|
|
$var wire 32 on" WORD_SIZE [31:0] $end
|
|
$var wire 120 {h" bank_addr [119:0] $end
|
|
$var wire 16 sh" bank_byteen [15:0] $end
|
|
$var wire 4 kh" bank_rw [3:0] $end
|
|
$var wire 42 ]i" bank_tag [41:0] $end
|
|
$var wire 4 %! bank_valids [3:0] $end
|
|
$var wire 128 =i" bank_writedata [127:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 1 Y/" o_empty $end
|
|
$var wire 1 [l out_empty $end
|
|
$var wire 120 ik out_per_addr [119:0] $end
|
|
$var wire 16 ak out_per_byteen [15:0] $end
|
|
$var wire 4 Yk out_per_rw [3:0] $end
|
|
$var wire 42 Kl out_per_tag [41:0] $end
|
|
$var wire 4 Qk out_per_valids [3:0] $end
|
|
$var wire 128 +l out_per_writedata [127:0] $end
|
|
$var wire 1 cl pop_qual $end
|
|
$var wire 1 1+ push_qual $end
|
|
$var wire 120 w." qual_addr [119:0] $end
|
|
$var wire 16 o." qual_byteen [15:0] $end
|
|
$var wire 1 )c qual_has_request $end
|
|
$var wire 2 1c qual_request_index [1:0] $end
|
|
$var wire 4 g." qual_rw [3:0] $end
|
|
$var wire 42 )}! qual_tag [41:0] $end
|
|
$var wire 4 _." qual_valids [3:0] $end
|
|
$var wire 128 9/" qual_writedata [127:0] $end
|
|
$var wire 4 kl real_out_per_valids [3:0] $end
|
|
$var wire 1 !c reqq_empty $end
|
|
$var wire 1 !}! reqq_full $end
|
|
$var wire 1 wb reqq_pop $end
|
|
$var wire 1 w* reqq_push $end
|
|
$var wire 30 Ic reqq_req_addr_st0 [29:0] $end
|
|
$var wire 4 Ac reqq_req_byteen_st0 [3:0] $end
|
|
$var wire 1 9c reqq_req_rw_st0 $end
|
|
$var wire 1 )c reqq_req_st0 $end
|
|
$var wire 42 )}! reqq_req_tag_st0 [41:0] $end
|
|
$var wire 2 1c reqq_req_tid_st0 [1:0] $end
|
|
$var wire 32 Qc reqq_req_writedata_st0 [31:0] $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 1 a/" use_empty $end
|
|
$var wire 120 w." use_per_addr [119:0] $end
|
|
$var wire 16 o." use_per_byteen [15:0] $end
|
|
$var wire 4 g." use_per_rw [3:0] $end
|
|
$var wire 42 )}! use_per_tag [41:0] $end
|
|
$var wire 4 _." use_per_valids [3:0] $end
|
|
$var wire 128 9/" use_per_writedata [127:0] $end
|
|
$scope module reqq_queue $end
|
|
$var wire 32 wn" BUFFERED_OUTPUT [31:0] $end
|
|
$var wire 32 yo" DATAW [31:0] $end
|
|
$var wire 32 on" SIZE [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 314 !' data_in [313:0] $end
|
|
$var wire 314 sl data_out [313:0] $end
|
|
$var wire 1 Y/" empty $end
|
|
$var wire 1 !}! full $end
|
|
$var wire 1 cl pop $end
|
|
$var wire 1 1+ push $end
|
|
$var wire 1 em reading $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 3 i/" size [2:0] $end
|
|
$var wire 3 i/" size_r [2:0] $end
|
|
$var wire 1 q' writing $end
|
|
$scope module genblk3 $end
|
|
$var wire 314 q/" data(0) [313:0] $end
|
|
$var wire 314 {/" data(1) [313:0] $end
|
|
$var wire 314 '0" data(2) [313:0] $end
|
|
$var wire 314 10" data(3) [313:0] $end
|
|
$scope module genblk2 $end
|
|
$var wire 1 55" bypass_r $end
|
|
$var wire 314 +4" curr_r [313:0] $end
|
|
$var wire 1 Y/" empty_r $end
|
|
$var wire 1 !}! full_r $end
|
|
$var wire 314 93" head_r [313:0] $end
|
|
$var wire 2 -5" rd_ptr_next_r [1:0] $end
|
|
$var wire 2 %5" rd_ptr_r [1:0] $end
|
|
$var wire 2 {4" wr_ptr_r [1:0] $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope module sel_bank $end
|
|
$var wire 32 on" N [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 2 1c grant_index [1:0] $end
|
|
$var wire 4 mm grant_onehot [3:0] $end
|
|
$var wire 1 )c grant_valid $end
|
|
$var wire 4 _." requests [3:0] $end
|
|
$var wire 1 [h" reset $end
|
|
$scope module genblk2 $end
|
|
$var wire 4 mm grant_onehot_r [3:0] $end
|
|
$scope module priority_encoder $end
|
|
$var wire 32 on" N [31:0] $end
|
|
$var wire 4 _." data_in [3:0] $end
|
|
$var wire 2 1c data_out [1:0] $end
|
|
$var wire 32 um i [31:0] $end
|
|
$var wire 1 )c valid_out $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope module cwb_queue $end
|
|
$var wire 32 wn" BUFFERED_OUTPUT [31:0] $end
|
|
$var wire 32 ;p" DATAW [31:0] $end
|
|
$var wire 32 on" SIZE [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 76 ct data_in [75:0] $end
|
|
$var wire 76 {t data_out [75:0] $end
|
|
$var wire 1 O"" empty $end
|
|
$var wire 1 W"" full $end
|
|
$var wire 1 !+ pop $end
|
|
$var wire 1 }i push $end
|
|
$var wire 1 y' reading $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 3 ]=" size [2:0] $end
|
|
$var wire 3 ]=" size_r [2:0] $end
|
|
$var wire 1 5u writing $end
|
|
$scope module genblk3 $end
|
|
$var wire 76 e=" data(0) [75:0] $end
|
|
$var wire 76 h=" data(1) [75:0] $end
|
|
$var wire 76 k=" data(2) [75:0] $end
|
|
$var wire 76 n=" data(3) [75:0] $end
|
|
$scope module genblk2 $end
|
|
$var wire 1 Q?" bypass_r $end
|
|
$var wire 76 !?" curr_r [75:0] $end
|
|
$var wire 1 O"" empty_r $end
|
|
$var wire 1 W"" full_r $end
|
|
$var wire 76 g>" head_r [75:0] $end
|
|
$var wire 2 I?" rd_ptr_next_r [1:0] $end
|
|
$var wire 2 A?" rd_ptr_r [1:0] $end
|
|
$var wire 2 9?" wr_ptr_r [1:0] $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope module dfp_queue $end
|
|
$var wire 32 wn" BUFFERED_OUTPUT [31:0] $end
|
|
$var wire 32 qo" DATAW [31:0] $end
|
|
$var wire 32 gn" SIZE [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 154 O& data_in [153:0] $end
|
|
$var wire 154 !k data_out [153:0] $end
|
|
$var wire 1 o|! empty $end
|
|
$var wire 1 w|! full $end
|
|
$var wire 1 Gb pop $end
|
|
$var wire 1 'n" push $end
|
|
$var wire 1 Ik reading $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 5 W&" size [4:0] $end
|
|
$var wire 5 W&" size_r [4:0] $end
|
|
$var wire 1 w& writing $end
|
|
$scope module genblk3 $end
|
|
$var wire 154 _&" data(0) [153:0] $end
|
|
$var wire 154 d&" data(1) [153:0] $end
|
|
$var wire 154 3'" data(10) [153:0] $end
|
|
$var wire 154 8'" data(11) [153:0] $end
|
|
$var wire 154 ='" data(12) [153:0] $end
|
|
$var wire 154 B'" data(13) [153:0] $end
|
|
$var wire 154 G'" data(14) [153:0] $end
|
|
$var wire 154 L'" data(15) [153:0] $end
|
|
$var wire 154 i&" data(2) [153:0] $end
|
|
$var wire 154 n&" data(3) [153:0] $end
|
|
$var wire 154 s&" data(4) [153:0] $end
|
|
$var wire 154 x&" data(5) [153:0] $end
|
|
$var wire 154 }&" data(6) [153:0] $end
|
|
$var wire 154 $'" data(7) [153:0] $end
|
|
$var wire 154 )'" data(8) [153:0] $end
|
|
$var wire 154 .'" data(9) [153:0] $end
|
|
$scope module genblk2 $end
|
|
$var wire 1 W." bypass_r $end
|
|
$var wire 154 u-" curr_r [153:0] $end
|
|
$var wire 1 o|! empty_r $end
|
|
$var wire 1 w|! full_r $end
|
|
$var wire 154 M-" head_r [153:0] $end
|
|
$var wire 4 O." rd_ptr_next_r [3:0] $end
|
|
$var wire 4 G." rd_ptr_r [3:0] $end
|
|
$var wire 4 ?." wr_ptr_r [3:0] $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope module dwb_queue $end
|
|
$var wire 32 wn" BUFFERED_OUTPUT [31:0] $end
|
|
$var wire 32 Cp" DATAW [31:0] $end
|
|
$var wire 32 on" SIZE [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 200 =u data_in [199:0] $end
|
|
$var wire 200 uu data_out [199:0] $end
|
|
$var wire 1 _"" empty $end
|
|
$var wire 1 g"" full $end
|
|
$var wire 1 )+ pop $end
|
|
$var wire 1 7j push $end
|
|
$var wire 1 #( reading $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 3 Y?" size [2:0] $end
|
|
$var wire 3 Y?" size_r [2:0] $end
|
|
$var wire 1 Ov writing $end
|
|
$scope module genblk3 $end
|
|
$var wire 200 a?" data(0) [199:0] $end
|
|
$var wire 200 h?" data(1) [199:0] $end
|
|
$var wire 200 o?" data(2) [199:0] $end
|
|
$var wire 200 v?" data(3) [199:0] $end
|
|
$scope module genblk2 $end
|
|
$var wire 1 QC" bypass_r $end
|
|
$var wire 200 _B" curr_r [199:0] $end
|
|
$var wire 1 _"" empty_r $end
|
|
$var wire 1 g"" full_r $end
|
|
$var wire 200 'B" head_r [199:0] $end
|
|
$var wire 2 IC" rd_ptr_next_r [1:0] $end
|
|
$var wire 2 AC" rd_ptr_r [1:0] $end
|
|
$var wire 2 9C" wr_ptr_r [1:0] $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope module s0_1_c0 $end
|
|
$var wire 32 #p" N [31:0] $end
|
|
$var wire 32 Wn" PASSTHRU [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 1 Io" flush $end
|
|
$var wire 243 }m in [242:0] $end
|
|
$var wire 243 =5" out [242:0] $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 1 Sd stall $end
|
|
$var wire 243 =5" value [242:0] $end
|
|
$upscope $end
|
|
$scope module snp_req_queue $end
|
|
$var wire 32 wn" BUFFERED_OUTPUT [31:0] $end
|
|
$var wire 32 io" DATAW [31:0] $end
|
|
$var wire 32 gn" SIZE [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 55 7& data_in [54:0] $end
|
|
$var wire 55 gj data_out [54:0] $end
|
|
$var wire 1 _|! empty $end
|
|
$var wire 1 g|! full $end
|
|
$var wire 1 'b pop $end
|
|
$var wire 1 /n" push $end
|
|
$var wire 1 wj reading $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 5 )#" size [4:0] $end
|
|
$var wire 5 )#" size_r [4:0] $end
|
|
$var wire 1 G& writing $end
|
|
$scope module genblk3 $end
|
|
$var wire 55 1#" data(0) [54:0] $end
|
|
$var wire 55 3#" data(1) [54:0] $end
|
|
$var wire 55 E#" data(10) [54:0] $end
|
|
$var wire 55 G#" data(11) [54:0] $end
|
|
$var wire 55 I#" data(12) [54:0] $end
|
|
$var wire 55 K#" data(13) [54:0] $end
|
|
$var wire 55 M#" data(14) [54:0] $end
|
|
$var wire 55 O#" data(15) [54:0] $end
|
|
$var wire 55 5#" data(2) [54:0] $end
|
|
$var wire 55 7#" data(3) [54:0] $end
|
|
$var wire 55 9#" data(4) [54:0] $end
|
|
$var wire 55 ;#" data(5) [54:0] $end
|
|
$var wire 55 =#" data(6) [54:0] $end
|
|
$var wire 55 ?#" data(7) [54:0] $end
|
|
$var wire 55 A#" data(8) [54:0] $end
|
|
$var wire 55 C#" data(9) [54:0] $end
|
|
$scope module genblk2 $end
|
|
$var wire 1 O&" bypass_r $end
|
|
$var wire 55 '&" curr_r [54:0] $end
|
|
$var wire 1 _|! empty_r $end
|
|
$var wire 1 g|! full_r $end
|
|
$var wire 55 u%" head_r [54:0] $end
|
|
$var wire 4 G&" rd_ptr_next_r [3:0] $end
|
|
$var wire 4 ?&" rd_ptr_r [3:0] $end
|
|
$var wire 4 7&" wr_ptr_r [3:0] $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope module st_1e_2 $end
|
|
$var wire 32 3p" N [31:0] $end
|
|
$var wire 32 Wn" PASSTHRU [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 1 Io" flush $end
|
|
$var wire 316 )s in [315:0] $end
|
|
$var wire 316 !7" out [315:0] $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 1 Sd stall $end
|
|
$var wire 316 !7" value [315:0] $end
|
|
$upscope $end
|
|
$scope module tag_data_access $end
|
|
$var wire 32 gn" BANK_LINE_SIZE [31:0] $end
|
|
$var wire 32 _n" CACHE_SIZE [31:0] $end
|
|
$var wire 32 wn" DRAM_ENABLE [31:0] $end
|
|
$var wire 32 on" NUM_BANKS [31:0] $end
|
|
$var wire 32 wn" STAGE_1_CYCLES [31:0] $end
|
|
$var wire 32 on" WORD_SIZE [31:0] $end
|
|
$var wire 32 wn" WRITE_ENABLE [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 128 {p data_write [127:0] $end
|
|
$var wire 1 yg dirty_st1e $end
|
|
$var wire 16 #h dirtyb_st1e [15:0] $end
|
|
$var wire 1 Sh fill_saw_dirty_st1e $end
|
|
$var wire 1 qg fill_sent $end
|
|
$var wire 1 'r force_core_miss $end
|
|
$var wire 1 #d force_request_miss_st1e $end
|
|
$var wire 1 =q invalidate_line $end
|
|
$var wire 1 [h is_snp_st1e $end
|
|
$var wire 4 Kh mem_byteen_st1e [3:0] $end
|
|
$var wire 1 Ch mem_rw_st1e $end
|
|
$var wire 1 qg miss_st1e $end
|
|
$var wire 1 sh mrvq_init_ready_state_st1e $end
|
|
$var wire 128 Cp qual_read_data_st1 [127:0] $end
|
|
$var wire 1 +p qual_read_dirty_st1 $end
|
|
$var wire 16 3p qual_read_dirtyb_st1 [15:0] $end
|
|
$var wire 20 ;p qual_read_tag_st1 [19:0] $end
|
|
$var wire 1 #p qual_read_valid_st1 $end
|
|
$var wire 128 ao read_data_st1c(0) [127:0] $end
|
|
$var wire 1 Io read_dirty_st1c(0) $end
|
|
$var wire 16 Qo read_dirtyb_st1c(0) [15:0] $end
|
|
$var wire 20 Yo read_tag_st1c(0) [19:0] $end
|
|
$var wire 1 Ao read_valid_st1c(0) $end
|
|
$var wire 6 _n readaddr_st10 [5:0] $end
|
|
$var wire 128 Ig readdata_st1e [127:0] $end
|
|
$var wire 20 ig readtag_st1e [19:0] $end
|
|
$var wire 32 Ag readword_st1e [31:0] $end
|
|
$var wire 1 }q real_miss $end
|
|
$var wire 1 Mq real_writefill $end
|
|
$var wire 1 mq req_invalid $end
|
|
$var wire 1 uq req_miss $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 1 eq should_write $end
|
|
$var wire 1 =q snoop_hit_no_pending $end
|
|
$var wire 1 ch snp_invalidate_st1e $end
|
|
$var wire 1 kh snp_to_mrvq_st1e $end
|
|
$var wire 1 Sd stall $end
|
|
$var wire 1 Sd stall_bank_pipe $end
|
|
$var wire 1 Eq tags_match $end
|
|
$var wire 128 Ig use_read_data_st1e [127:0] $end
|
|
$var wire 1 kp use_read_dirty_st1e $end
|
|
$var wire 16 #h use_read_dirtyb_st1e [15:0] $end
|
|
$var wire 20 ig use_read_tag_st1e [19:0] $end
|
|
$var wire 1 cp use_read_valid_st1e $end
|
|
$var wire 128 {p use_write_data [127:0] $end
|
|
$var wire 16 sp use_write_enable [15:0] $end
|
|
$var wire 1 %i valid_req_st1e $end
|
|
$var wire 16 ]q we [15:0] $end
|
|
$var wire 2 9o wordsel_st1e [1:0] $end
|
|
$var wire 26 =i writeaddr_st1e [25:0] $end
|
|
$var wire 128 wn writedata_st1e [127:0] $end
|
|
$var wire 1 gn writefill_st1e $end
|
|
$var wire 6 _n writeladdr_st1e [5:0] $end
|
|
$var wire 20 Uq writetag_st1e [19:0] $end
|
|
$var wire 32 on writeword_st1e [31:0] $end
|
|
$scope module genblk4(0) $end
|
|
$var wire 1 /r normal_write $end
|
|
$upscope $end
|
|
$scope module genblk4(1) $end
|
|
$var wire 1 7r normal_write $end
|
|
$upscope $end
|
|
$scope module genblk4(2) $end
|
|
$var wire 1 ?r normal_write $end
|
|
$upscope $end
|
|
$scope module genblk4(3) $end
|
|
$var wire 1 Gr normal_write $end
|
|
$upscope $end
|
|
$scope module s0_1_c0 $end
|
|
$var wire 32 +p" N [31:0] $end
|
|
$var wire 32 wn" PASSTHRU [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 1 Io" flush $end
|
|
$var wire 166 Wr in [165:0] $end
|
|
$var wire 166 Wr out [165:0] $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 1 Sd stall $end
|
|
$var wire 166 O6" value [165:0] $end
|
|
$upscope $end
|
|
$scope module tag_data_structure $end
|
|
$var wire 32 gn" BANK_LINE_SIZE [31:0] $end
|
|
$var wire 32 _n" CACHE_SIZE [31:0] $end
|
|
$var wire 32 on" NUM_BANKS [31:0] $end
|
|
$var wire 32 on" WORD_SIZE [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 64 }5" dirty [63:0] $end
|
|
$var wire 1 Or do_write $end
|
|
$var wire 1 qg fill_sent $end
|
|
$var wire 32 ?6" i [31:0] $end
|
|
$var wire 1 =q invalidate $end
|
|
$var wire 32 G6" j [31:0] $end
|
|
$var wire 6 _n read_addr [5:0] $end
|
|
$var wire 128 Cp read_data [127:0] $end
|
|
$var wire 1 +p read_dirty $end
|
|
$var wire 16 3p read_dirtyb [15:0] $end
|
|
$var wire 20 ;p read_tag [19:0] $end
|
|
$var wire 1 #p read_valid $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 1 Sd stall_bank_pipe $end
|
|
$var wire 20 Uq tag_index [19:0] $end
|
|
$var wire 64 /6" valid [63:0] $end
|
|
$var wire 6 _n write_addr [5:0] $end
|
|
$var wire 128 {p write_data [127:0] $end
|
|
$var wire 16 sp write_enable [15:0] $end
|
|
$var wire 1 Mq write_fill $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope module genblk5(3) $end
|
|
$var wire 120 {h" curr_bank_core_req_addr [119:0] $end
|
|
$var wire 16 sh" curr_bank_core_req_byteen [15:0] $end
|
|
$var wire 128 =i" curr_bank_core_req_data [127:0] $end
|
|
$var wire 1 k.! curr_bank_core_req_ready $end
|
|
$var wire 4 kh" curr_bank_core_req_rw [3:0] $end
|
|
$var wire 42 ]i" curr_bank_core_req_tag [41:0] $end
|
|
$var wire 4 E! curr_bank_core_req_valid [3:0] $end
|
|
$var wire 32 A3 curr_bank_core_rsp_data [31:0] $end
|
|
$var wire 1 M! curr_bank_core_rsp_ready $end
|
|
$var wire 42 I3 curr_bank_core_rsp_tag [41:0] $end
|
|
$var wire 2 93 curr_bank_core_rsp_tid [1:0] $end
|
|
$var wire 1 K.! curr_bank_core_rsp_valid $end
|
|
$var wire 26 [.! curr_bank_dram_fill_req_addr [25:0] $end
|
|
$var wire 1 )-! curr_bank_dram_fill_req_ready $end
|
|
$var wire 1 Y3 curr_bank_dram_fill_req_valid $end
|
|
$var wire 26 ]m" curr_bank_dram_fill_rsp_addr [25:0] $end
|
|
$var wire 128 Qk" curr_bank_dram_fill_rsp_data [127:0] $end
|
|
$var wire 1 S.! curr_bank_dram_fill_rsp_ready $end
|
|
$var wire 1 7n" curr_bank_dram_fill_rsp_valid $end
|
|
$var wire 26 q3 curr_bank_dram_wb_req_addr [25:0] $end
|
|
$var wire 16 i3 curr_bank_dram_wb_req_byteen [15:0] $end
|
|
$var wire 128 y3 curr_bank_dram_wb_req_data [127:0] $end
|
|
$var wire 1 U! curr_bank_dram_wb_req_ready $end
|
|
$var wire 1 a3 curr_bank_dram_wb_req_valid $end
|
|
$var wire 26 mm" curr_bank_snp_req_addr [25:0] $end
|
|
$var wire 1 3l" curr_bank_snp_req_invalidate $end
|
|
$var wire 1 c.! curr_bank_snp_req_ready $end
|
|
$var wire 28 ;l" curr_bank_snp_req_tag [27:0] $end
|
|
$var wire 1 ?n" curr_bank_snp_req_valid $end
|
|
$var wire 1 ]! curr_bank_snp_rsp_ready $end
|
|
$var wire 28 C4 curr_bank_snp_rsp_tag [27:0] $end
|
|
$var wire 1 ;4 curr_bank_snp_rsp_valid $end
|
|
$scope module bank $end
|
|
$var wire 32 Sp" BANK_ID [31:0] $end
|
|
$var wire 32 gn" BANK_LINE_SIZE [31:0] $end
|
|
$var wire 32 Wn" CACHE_ID [31:0] $end
|
|
$var wire 32 _n" CACHE_SIZE [31:0] $end
|
|
$var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end
|
|
$var wire 32 !o" CORE_TAG_WIDTH [31:0] $end
|
|
$var wire 32 on" CREQ_SIZE [31:0] $end
|
|
$var wire 32 on" CWBQ_SIZE [31:0] $end
|
|
$var wire 32 gn" DFPQ_SIZE [31:0] $end
|
|
$var wire 32 on" DFQQ_SIZE [31:0] $end
|
|
$var wire 32 wn" DRAM_ENABLE [31:0] $end
|
|
$var wire 32 on" DWBQ_SIZE [31:0] $end
|
|
$var wire 32 gn" MRVQ_SIZE [31:0] $end
|
|
$var wire 32 on" NUM_BANKS [31:0] $end
|
|
$var wire 32 on" NUM_REQUESTS [31:0] $end
|
|
$var wire 32 Wn" SNOOP_FORWARDING [31:0] $end
|
|
$var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end
|
|
$var wire 32 gn" SNRQ_SIZE [31:0] $end
|
|
$var wire 32 wn" STAGE_1_CYCLES [31:0] $end
|
|
$var wire 32 on" WORD_SIZE [31:0] $end
|
|
$var wire 32 wn" WRITE_ENABLE [31:0] $end
|
|
$var wire 26 oz addr_st1(0) [25:0] $end
|
|
$var wire 26 m} addr_st1e [25:0] $end
|
|
$var wire 26 [.! addr_st2 [25:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 120 {h" core_req_addr [119:0] $end
|
|
$var wire 16 sh" core_req_byteen [15:0] $end
|
|
$var wire 128 =i" core_req_data [127:0] $end
|
|
$var wire 1 k.! core_req_ready $end
|
|
$var wire 4 kh" core_req_rw [3:0] $end
|
|
$var wire 42 ]i" core_req_tag [41:0] $end
|
|
$var wire 4 E! core_req_valid [3:0] $end
|
|
$var wire 32 A3 core_rsp_data [31:0] $end
|
|
$var wire 1 M! core_rsp_ready $end
|
|
$var wire 42 I3 core_rsp_tag [41:0] $end
|
|
$var wire 2 93 core_rsp_tid [1:0] $end
|
|
$var wire 1 K.! core_rsp_valid $end
|
|
$var wire 32 uE" cwbq_data [31:0] $end
|
|
$var wire 1 IG" cwbq_empty $end
|
|
$var wire 1 QG" cwbq_full $end
|
|
$var wire 1 A+ cwbq_pop $end
|
|
$var wire 1 O~ cwbq_push $end
|
|
$var wire 1 kx cwbq_push_stall $end
|
|
$var wire 1 W~ cwbq_push_unqual $end
|
|
$var wire 42 5E" cwbq_tag [41:0] $end
|
|
$var wire 2 -E" cwbq_tid [1:0] $end
|
|
$var wire 26 !w dfpq_addr_st0 [25:0] $end
|
|
$var wire 1 iC" dfpq_empty $end
|
|
$var wire 128 )w dfpq_filldata_st0 [127:0] $end
|
|
$var wire 1 qC" dfpq_full $end
|
|
$var wire 1 wv dfpq_pop $end
|
|
$var wire 1 Ey dfpq_pop_unqual $end
|
|
$var wire 1 K| dirty_st1e $end
|
|
$var wire 1 GF" dirty_st2 $end
|
|
$var wire 16 S| dirtyb_st1e [15:0] $end
|
|
$var wire 16 OF" dirtyb_st2 [15:0] $end
|
|
$var wire 26 [.! dram_fill_req_addr [25:0] $end
|
|
$var wire 1 7~ dram_fill_req_fast $end
|
|
$var wire 1 )-! dram_fill_req_ready $end
|
|
$var wire 1 {x dram_fill_req_stall $end
|
|
$var wire 1 _~ dram_fill_req_unqual $end
|
|
$var wire 1 Y3 dram_fill_req_valid $end
|
|
$var wire 26 ]m" dram_fill_rsp_addr [25:0] $end
|
|
$var wire 128 Qk" dram_fill_rsp_data [127:0] $end
|
|
$var wire 1 S.! dram_fill_rsp_ready $end
|
|
$var wire 1 7n" dram_fill_rsp_valid $end
|
|
$var wire 26 q3 dram_wb_req_addr [25:0] $end
|
|
$var wire 16 i3 dram_wb_req_byteen [15:0] $end
|
|
$var wire 128 y3 dram_wb_req_data [127:0] $end
|
|
$var wire 1 +( dram_wb_req_fire $end
|
|
$var wire 1 U! dram_wb_req_ready $end
|
|
$var wire 1 a3 dram_wb_req_valid $end
|
|
$var wire 1 yG" dwbq_dual_valid_sel $end
|
|
$var wire 1 YG" dwbq_empty $end
|
|
$var wire 1 aG" dwbq_full $end
|
|
$var wire 1 o~ dwbq_is_dwb_in $end
|
|
$var wire 1 !!! dwbq_is_dwb_out $end
|
|
$var wire 1 w~ dwbq_is_snp_in $end
|
|
$var wire 1 )!! dwbq_is_snp_out $end
|
|
$var wire 1 I+ dwbq_pop $end
|
|
$var wire 1 g~ dwbq_push $end
|
|
$var wire 1 sx dwbq_push_stall $end
|
|
$var wire 1 1!! dwbq_push_unqual $end
|
|
$var wire 26 iG" dwbq_req_addr [25:0] $end
|
|
$var wire 1 %} fill_saw_dirty_st1e $end
|
|
$var wire 1 oF" fill_saw_dirty_st2 $end
|
|
$var wire 1 Sx force_request_miss_st1e $end
|
|
$var wire 1 =y going_to_write_st1(0) $end
|
|
$var wire 49 ){ inst_meta_st1(0) [48:0] $end
|
|
$var wire 49 WF" inst_meta_st2 [48:0] $end
|
|
$var wire 1 -y is_fill_in_pipe $end
|
|
$var wire 1 5y is_fill_st1(0) $end
|
|
$var wire 1 UE" is_fill_st2 $end
|
|
$var wire 1 i{ is_mrvq_st1(0) $end
|
|
$var wire 1 ]} is_mrvq_st1e $end
|
|
$var wire 1 ]} is_mrvq_st1e_st2 $end
|
|
$var wire 1 1G" is_mrvq_st2 $end
|
|
$var wire 1 Y{ is_snp_st1(0) $end
|
|
$var wire 1 -} is_snp_st1e $end
|
|
$var wire 1 wF" is_snp_st2 $end
|
|
$var wire 32 ao" j [31:0] $end
|
|
$var wire 4 {| mem_byteen_st1e [3:0] $end
|
|
$var wire 1 s| mem_rw_st1e $end
|
|
$var wire 1 ?~ miss_add $end
|
|
$var wire 26 [.! miss_add_addr [25:0] $end
|
|
$var wire 1 M} miss_add_because_miss $end
|
|
$var wire 1 )G" miss_add_because_pending $end
|
|
$var wire 4 ME" miss_add_byteen [3:0] $end
|
|
$var wire 32 mE" miss_add_data [31:0] $end
|
|
$var wire 1 G~ miss_add_is_mrvq $end
|
|
$var wire 1 wF" miss_add_is_snp $end
|
|
$var wire 1 EE" miss_add_rw $end
|
|
$var wire 1 !G" miss_add_snp_invalidate $end
|
|
$var wire 42 5E" miss_add_tag [41:0] $end
|
|
$var wire 2 -E" miss_add_tid [1:0] $end
|
|
$var wire 1 7~ miss_add_unqual $end
|
|
$var wire 2 eE" miss_add_wsel [1:0] $end
|
|
$var wire 1 C| miss_st1e $end
|
|
$var wire 1 ?F" miss_st2 $end
|
|
$var wire 26 KD" mrvq_addr_st0 [25:0] $end
|
|
$var wire 4 sD" mrvq_byteen_st0 [3:0] $end
|
|
$var wire 1 3D" mrvq_full $end
|
|
$var wire 1 '~ mrvq_init_ready_state_hazard_st0_st1 $end
|
|
$var wire 1 /~ mrvq_init_ready_state_hazard_st1e_st1 $end
|
|
$var wire 1 E} mrvq_init_ready_state_st1e $end
|
|
$var wire 1 }} mrvq_init_ready_state_st2 $end
|
|
$var wire 1 AG" mrvq_init_ready_state_unqual_st2 $end
|
|
$var wire 1 {D" mrvq_is_snp_st0 $end
|
|
$var wire 1 Cx mrvq_pending_hazard_st1e $end
|
|
$var wire 1 +x mrvq_pop $end
|
|
$var wire 1 3x mrvq_pop_unqual $end
|
|
$var wire 1 cx mrvq_push_stall $end
|
|
$var wire 1 e} mrvq_recover_ready_state_st1e $end
|
|
$var wire 1 9G" mrvq_recover_ready_state_st2 $end
|
|
$var wire 1 ;x mrvq_rw_st0 $end
|
|
$var wire 1 %E" mrvq_snp_invalidate_st0 $end
|
|
$var wire 1 ;D" mrvq_stop $end
|
|
$var wire 42 cD" mrvq_tag_st0 [41:0] $end
|
|
$var wire 2 CD" mrvq_tid_st0 [1:0] $end
|
|
$var wire 1 3x mrvq_valid_st0 $end
|
|
$var wire 32 [D" mrvq_writeword_st0 [31:0] $end
|
|
$var wire 2 SD" mrvq_wsel_st0 [1:0] $end
|
|
$var wire 26 ey qual_addr_st0 [25:0] $end
|
|
$var wire 1 Oz qual_going_to_write_st0 $end
|
|
$var wire 49 ?z qual_inst_meta_st0 [48:0] $end
|
|
$var wire 1 Ey qual_is_fill_st0 $end
|
|
$var wire 1 3x qual_is_mrvq_st0 $end
|
|
$var wire 1 Wz qual_is_snp_st0 $end
|
|
$var wire 1 _z qual_snp_invalidate_st0 $end
|
|
$var wire 1 ]y qual_valid_st0 $end
|
|
$var wire 1 u} qual_valid_st1e_2 $end
|
|
$var wire 128 }y qual_writedata_st0 [127:0] $end
|
|
$var wire 32 uy qual_writeword_st0 [31:0] $end
|
|
$var wire 2 my qual_wsel_st0 [1:0] $end
|
|
$var wire 128 y{ readdata_st1e [127:0] $end
|
|
$var wire 128 }E" readdata_st2 [127:0] $end
|
|
$var wire 20 ;| readtag_st1e [19:0] $end
|
|
$var wire 20 gF" readtag_st2 [19:0] $end
|
|
$var wire 32 q{ readword_st1e [31:0] $end
|
|
$var wire 32 uE" readword_st2 [31:0] $end
|
|
$var wire 1 [x recover_mrvq_state_st2 $end
|
|
$var wire 1 Qw reqq_empty $end
|
|
$var wire 1 yC" reqq_full $end
|
|
$var wire 1 Iw reqq_pop $end
|
|
$var wire 1 My reqq_pop_unqual $end
|
|
$var wire 1 9+ reqq_push $end
|
|
$var wire 30 yw reqq_req_addr_st0 [29:0] $end
|
|
$var wire 4 qw reqq_req_byteen_st0 [3:0] $end
|
|
$var wire 1 iw reqq_req_rw_st0 $end
|
|
$var wire 1 Yw reqq_req_st0 $end
|
|
$var wire 42 #D" reqq_req_tag_st0 [41:0] $end
|
|
$var wire 2 aw reqq_req_tid_st0 [1:0] $end
|
|
$var wire 32 #x reqq_req_writeword_st0 [31:0] $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 1 a{ snp_invalidate_st1(0) $end
|
|
$var wire 1 5} snp_invalidate_st1e $end
|
|
$var wire 1 !G" snp_invalidate_st2 $end
|
|
$var wire 26 mm" snp_req_addr [25:0] $end
|
|
$var wire 1 3l" snp_req_invalidate $end
|
|
$var wire 1 c.! snp_req_ready $end
|
|
$var wire 28 ;l" snp_req_tag [27:0] $end
|
|
$var wire 1 ?n" snp_req_valid $end
|
|
$var wire 1 3( snp_rsp_fire $end
|
|
$var wire 1 ]! snp_rsp_ready $end
|
|
$var wire 28 C4 snp_rsp_tag [27:0] $end
|
|
$var wire 1 ;4 snp_rsp_valid $end
|
|
$var wire 1 =} snp_to_mrvq_st1e $end
|
|
$var wire 1 )G" snp_to_mrvq_st2 $end
|
|
$var wire 26 _v snrq_addr_st0 [25:0] $end
|
|
$var wire 1 YC" snrq_empty $end
|
|
$var wire 1 aC" snrq_full $end
|
|
$var wire 1 gv snrq_invalidate_st0 $end
|
|
$var wire 1 Wv snrq_pop $end
|
|
$var wire 1 Uy snrq_pop_unqual $end
|
|
$var wire 28 ov snrq_tag_st0 [27:0] $end
|
|
$var wire 28 qG" snrq_tag_st2 [27:0] $end
|
|
$var wire 1 Kx st2_pending_hazard_st1e $end
|
|
$var wire 1 %y stall_bank_pipe $end
|
|
$var wire 42 [| tag_st1e [41:0] $end
|
|
$var wire 2 k| tid_st1e [1:0] $end
|
|
$var wire 1 gz valid_st1(0) $end
|
|
$var wire 1 U} valid_st1e $end
|
|
$var wire 1 ]E" valid_st2 $end
|
|
$var wire 128 9{ writedata_st1(0) [127:0] $end
|
|
$var wire 32 !{ writeword_st1(0) [31:0] $end
|
|
$var wire 32 mE" writeword_st2 [31:0] $end
|
|
$var wire 2 wz wsel_st1(0) [1:0] $end
|
|
$var wire 2 eE" wsel_st2 [1:0] $end
|
|
$scope module cache_miss_resrv $end
|
|
$var wire 32 Sp" BANK_ID [31:0] $end
|
|
$var wire 32 gn" BANK_LINE_SIZE [31:0] $end
|
|
$var wire 32 Wn" CACHE_ID [31:0] $end
|
|
$var wire 32 !o" CORE_TAG_WIDTH [31:0] $end
|
|
$var wire 32 gn" MRVQ_SIZE [31:0] $end
|
|
$var wire 32 on" NUM_BANKS [31:0] $end
|
|
$var wire 32 on" NUM_REQUESTS [31:0] $end
|
|
$var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end
|
|
$var wire 32 on" WORD_SIZE [31:0] $end
|
|
$var wire 416 s`" addr_table [415:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 4 /b" dequeue_index [3:0] $end
|
|
$var wire 1 3x dequeue_possible $end
|
|
$var wire 4 ?b" enqueue_index [3:0] $end
|
|
$var wire 1 Ob" enqueue_possible $end
|
|
$var wire 26 m} fill_addr_st1 [25:0] $end
|
|
$var wire 4 7b" head_ptr [3:0] $end
|
|
$var wire 1 {*! increment_head $end
|
|
$var wire 1 9%! is_fill_st1 $end
|
|
$var wire 1 G~ is_mrvq $end
|
|
$var wire 16 K*! make_ready [15:0] $end
|
|
$var wire 16 S*! make_ready_push [15:0] $end
|
|
$var wire 85 k\" metadata_table(0) [84:0] $end
|
|
$var wire 85 n\" metadata_table(1) [84:0] $end
|
|
$var wire 85 +]" metadata_table(10) [84:0] $end
|
|
$var wire 85 .]" metadata_table(11) [84:0] $end
|
|
$var wire 85 1]" metadata_table(12) [84:0] $end
|
|
$var wire 85 4]" metadata_table(13) [84:0] $end
|
|
$var wire 85 7]" metadata_table(14) [84:0] $end
|
|
$var wire 85 :]" metadata_table(15) [84:0] $end
|
|
$var wire 85 q\" metadata_table(2) [84:0] $end
|
|
$var wire 85 t\" metadata_table(3) [84:0] $end
|
|
$var wire 85 w\" metadata_table(4) [84:0] $end
|
|
$var wire 85 z\" metadata_table(5) [84:0] $end
|
|
$var wire 85 }\" metadata_table(6) [84:0] $end
|
|
$var wire 85 "]" metadata_table(7) [84:0] $end
|
|
$var wire 85 %]" metadata_table(8) [84:0] $end
|
|
$var wire 85 (]" metadata_table(9) [84:0] $end
|
|
$var wire 1 ?~ miss_add $end
|
|
$var wire 26 [.! miss_add_addr [25:0] $end
|
|
$var wire 4 ME" miss_add_byteen [3:0] $end
|
|
$var wire 32 mE" miss_add_data [31:0] $end
|
|
$var wire 1 wF" miss_add_is_snp $end
|
|
$var wire 1 EE" miss_add_rw $end
|
|
$var wire 1 !G" miss_add_snp_invalidate $end
|
|
$var wire 42 5E" miss_add_tag [41:0] $end
|
|
$var wire 2 -E" miss_add_tid [1:0] $end
|
|
$var wire 2 eE" miss_add_wsel [1:0] $end
|
|
$var wire 26 KD" miss_resrv_addr_st0 [25:0] $end
|
|
$var wire 4 sD" miss_resrv_byteen_st0 [3:0] $end
|
|
$var wire 32 [D" miss_resrv_data_st0 [31:0] $end
|
|
$var wire 1 3D" miss_resrv_full $end
|
|
$var wire 1 {D" miss_resrv_is_snp_st0 $end
|
|
$var wire 1 +x miss_resrv_pop $end
|
|
$var wire 1 ;x miss_resrv_rw_st0 $end
|
|
$var wire 1 %E" miss_resrv_snp_invalidate_st0 $end
|
|
$var wire 1 ;D" miss_resrv_stop $end
|
|
$var wire 42 cD" miss_resrv_tag_st0 [41:0] $end
|
|
$var wire 2 CD" miss_resrv_tid_st0 [1:0] $end
|
|
$var wire 1 3x miss_resrv_valid_st0 $end
|
|
$var wire 2 SD" miss_resrv_wsel_st0 [1:0] $end
|
|
$var wire 1 }} mrvq_init_ready_state $end
|
|
$var wire 1 k*! mrvq_pop $end
|
|
$var wire 1 c*! mrvq_push $end
|
|
$var wire 1 Cx pending_hazard $end
|
|
$var wire 1 -+! qual_mrvq_init $end
|
|
$var wire 16 'b" ready_table [15:0] $end
|
|
$var wire 1 s*! recover_state $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 4 /b" schedule_ptr [3:0] $end
|
|
$var wire 5 Gb" size [4:0] $end
|
|
$var wire 4 ?b" tail_ptr [3:0] $end
|
|
$var wire 1 %+! update_ready $end
|
|
$var wire 16 [*! valid_address_match [15:0] $end
|
|
$var wire 16 }a" valid_table [15:0] $end
|
|
$upscope $end
|
|
$scope module core_req_arb $end
|
|
$var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end
|
|
$var wire 32 !o" CORE_TAG_WIDTH [31:0] $end
|
|
$var wire 32 on" CREQ_SIZE [31:0] $end
|
|
$var wire 32 on" NUM_REQUESTS [31:0] $end
|
|
$var wire 32 on" WORD_SIZE [31:0] $end
|
|
$var wire 120 {h" bank_addr [119:0] $end
|
|
$var wire 16 sh" bank_byteen [15:0] $end
|
|
$var wire 4 kh" bank_rw [3:0] $end
|
|
$var wire 42 ]i" bank_tag [41:0] $end
|
|
$var wire 4 E! bank_valids [3:0] $end
|
|
$var wire 128 =i" bank_writedata [127:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 1 ST" o_empty $end
|
|
$var wire 1 -#! out_empty $end
|
|
$var wire 120 ;"! out_per_addr [119:0] $end
|
|
$var wire 16 3"! out_per_byteen [15:0] $end
|
|
$var wire 4 +"! out_per_rw [3:0] $end
|
|
$var wire 42 {"! out_per_tag [41:0] $end
|
|
$var wire 4 #"! out_per_valids [3:0] $end
|
|
$var wire 128 ["! out_per_writedata [127:0] $end
|
|
$var wire 1 5#! pop_qual $end
|
|
$var wire 1 Q+ push_qual $end
|
|
$var wire 120 qS" qual_addr [119:0] $end
|
|
$var wire 16 iS" qual_byteen [15:0] $end
|
|
$var wire 1 Yw qual_has_request $end
|
|
$var wire 2 aw qual_request_index [1:0] $end
|
|
$var wire 4 aS" qual_rw [3:0] $end
|
|
$var wire 42 #D" qual_tag [41:0] $end
|
|
$var wire 4 YS" qual_valids [3:0] $end
|
|
$var wire 128 3T" qual_writedata [127:0] $end
|
|
$var wire 4 =#! real_out_per_valids [3:0] $end
|
|
$var wire 1 Qw reqq_empty $end
|
|
$var wire 1 yC" reqq_full $end
|
|
$var wire 1 Iw reqq_pop $end
|
|
$var wire 1 9+ reqq_push $end
|
|
$var wire 30 yw reqq_req_addr_st0 [29:0] $end
|
|
$var wire 4 qw reqq_req_byteen_st0 [3:0] $end
|
|
$var wire 1 iw reqq_req_rw_st0 $end
|
|
$var wire 1 Yw reqq_req_st0 $end
|
|
$var wire 42 #D" reqq_req_tag_st0 [41:0] $end
|
|
$var wire 2 aw reqq_req_tid_st0 [1:0] $end
|
|
$var wire 32 #x reqq_req_writedata_st0 [31:0] $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 1 [T" use_empty $end
|
|
$var wire 120 qS" use_per_addr [119:0] $end
|
|
$var wire 16 iS" use_per_byteen [15:0] $end
|
|
$var wire 4 aS" use_per_rw [3:0] $end
|
|
$var wire 42 #D" use_per_tag [41:0] $end
|
|
$var wire 4 YS" use_per_valids [3:0] $end
|
|
$var wire 128 3T" use_per_writedata [127:0] $end
|
|
$scope module reqq_queue $end
|
|
$var wire 32 wn" BUFFERED_OUTPUT [31:0] $end
|
|
$var wire 32 yo" DATAW [31:0] $end
|
|
$var wire 32 on" SIZE [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 314 %) data_in [313:0] $end
|
|
$var wire 314 E#! data_out [313:0] $end
|
|
$var wire 1 ST" empty $end
|
|
$var wire 1 yC" full $end
|
|
$var wire 1 5#! pop $end
|
|
$var wire 1 Q+ push $end
|
|
$var wire 1 7$! reading $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 3 cT" size [2:0] $end
|
|
$var wire 3 cT" size_r [2:0] $end
|
|
$var wire 1 u) writing $end
|
|
$scope module genblk3 $end
|
|
$var wire 314 kT" data(0) [313:0] $end
|
|
$var wire 314 uT" data(1) [313:0] $end
|
|
$var wire 314 !U" data(2) [313:0] $end
|
|
$var wire 314 +U" data(3) [313:0] $end
|
|
$scope module genblk2 $end
|
|
$var wire 1 /Z" bypass_r $end
|
|
$var wire 314 %Y" curr_r [313:0] $end
|
|
$var wire 1 ST" empty_r $end
|
|
$var wire 1 yC" full_r $end
|
|
$var wire 314 3X" head_r [313:0] $end
|
|
$var wire 2 'Z" rd_ptr_next_r [1:0] $end
|
|
$var wire 2 }Y" rd_ptr_r [1:0] $end
|
|
$var wire 2 uY" wr_ptr_r [1:0] $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope module sel_bank $end
|
|
$var wire 32 on" N [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 2 aw grant_index [1:0] $end
|
|
$var wire 4 ?$! grant_onehot [3:0] $end
|
|
$var wire 1 Yw grant_valid $end
|
|
$var wire 4 YS" requests [3:0] $end
|
|
$var wire 1 [h" reset $end
|
|
$scope module genblk2 $end
|
|
$var wire 4 ?$! grant_onehot_r [3:0] $end
|
|
$scope module priority_encoder $end
|
|
$var wire 32 on" N [31:0] $end
|
|
$var wire 4 YS" data_in [3:0] $end
|
|
$var wire 2 aw data_out [1:0] $end
|
|
$var wire 32 G$! i [31:0] $end
|
|
$var wire 1 Yw valid_out $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope module cwb_queue $end
|
|
$var wire 32 wn" BUFFERED_OUTPUT [31:0] $end
|
|
$var wire 32 ;p" DATAW [31:0] $end
|
|
$var wire 32 on" SIZE [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 76 5+! data_in [75:0] $end
|
|
$var wire 76 M+! data_out [75:0] $end
|
|
$var wire 1 IG" empty $end
|
|
$var wire 1 QG" full $end
|
|
$var wire 1 A+ pop $end
|
|
$var wire 1 O~ push $end
|
|
$var wire 1 }) reading $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 3 Wb" size [2:0] $end
|
|
$var wire 3 Wb" size_r [2:0] $end
|
|
$var wire 1 e+! writing $end
|
|
$scope module genblk3 $end
|
|
$var wire 76 _b" data(0) [75:0] $end
|
|
$var wire 76 bb" data(1) [75:0] $end
|
|
$var wire 76 eb" data(2) [75:0] $end
|
|
$var wire 76 hb" data(3) [75:0] $end
|
|
$scope module genblk2 $end
|
|
$var wire 1 Kd" bypass_r $end
|
|
$var wire 76 yc" curr_r [75:0] $end
|
|
$var wire 1 IG" empty_r $end
|
|
$var wire 1 QG" full_r $end
|
|
$var wire 76 ac" head_r [75:0] $end
|
|
$var wire 2 Cd" rd_ptr_next_r [1:0] $end
|
|
$var wire 2 ;d" rd_ptr_r [1:0] $end
|
|
$var wire 2 3d" wr_ptr_r [1:0] $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope module dfp_queue $end
|
|
$var wire 32 wn" BUFFERED_OUTPUT [31:0] $end
|
|
$var wire 32 qo" DATAW [31:0] $end
|
|
$var wire 32 gn" SIZE [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 154 S( data_in [153:0] $end
|
|
$var wire 154 Q!! data_out [153:0] $end
|
|
$var wire 1 iC" empty $end
|
|
$var wire 1 qC" full $end
|
|
$var wire 1 wv pop $end
|
|
$var wire 1 7n" push $end
|
|
$var wire 1 y!! reading $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 5 QK" size [4:0] $end
|
|
$var wire 5 QK" size_r [4:0] $end
|
|
$var wire 1 {( writing $end
|
|
$scope module genblk3 $end
|
|
$var wire 154 YK" data(0) [153:0] $end
|
|
$var wire 154 ^K" data(1) [153:0] $end
|
|
$var wire 154 -L" data(10) [153:0] $end
|
|
$var wire 154 2L" data(11) [153:0] $end
|
|
$var wire 154 7L" data(12) [153:0] $end
|
|
$var wire 154 <L" data(13) [153:0] $end
|
|
$var wire 154 AL" data(14) [153:0] $end
|
|
$var wire 154 FL" data(15) [153:0] $end
|
|
$var wire 154 cK" data(2) [153:0] $end
|
|
$var wire 154 hK" data(3) [153:0] $end
|
|
$var wire 154 mK" data(4) [153:0] $end
|
|
$var wire 154 rK" data(5) [153:0] $end
|
|
$var wire 154 wK" data(6) [153:0] $end
|
|
$var wire 154 |K" data(7) [153:0] $end
|
|
$var wire 154 #L" data(8) [153:0] $end
|
|
$var wire 154 (L" data(9) [153:0] $end
|
|
$scope module genblk2 $end
|
|
$var wire 1 QS" bypass_r $end
|
|
$var wire 154 oR" curr_r [153:0] $end
|
|
$var wire 1 iC" empty_r $end
|
|
$var wire 1 qC" full_r $end
|
|
$var wire 154 GR" head_r [153:0] $end
|
|
$var wire 4 IS" rd_ptr_next_r [3:0] $end
|
|
$var wire 4 AS" rd_ptr_r [3:0] $end
|
|
$var wire 4 9S" wr_ptr_r [3:0] $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope module dwb_queue $end
|
|
$var wire 32 wn" BUFFERED_OUTPUT [31:0] $end
|
|
$var wire 32 Cp" DATAW [31:0] $end
|
|
$var wire 32 on" SIZE [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 200 m+! data_in [199:0] $end
|
|
$var wire 200 G,! data_out [199:0] $end
|
|
$var wire 1 YG" empty $end
|
|
$var wire 1 aG" full $end
|
|
$var wire 1 I+ pop $end
|
|
$var wire 1 g~ push $end
|
|
$var wire 1 '* reading $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 3 Sd" size [2:0] $end
|
|
$var wire 3 Sd" size_r [2:0] $end
|
|
$var wire 1 !-! writing $end
|
|
$scope module genblk3 $end
|
|
$var wire 200 [d" data(0) [199:0] $end
|
|
$var wire 200 bd" data(1) [199:0] $end
|
|
$var wire 200 id" data(2) [199:0] $end
|
|
$var wire 200 pd" data(3) [199:0] $end
|
|
$scope module genblk2 $end
|
|
$var wire 1 Kh" bypass_r $end
|
|
$var wire 200 Yg" curr_r [199:0] $end
|
|
$var wire 1 YG" empty_r $end
|
|
$var wire 1 aG" full_r $end
|
|
$var wire 200 !g" head_r [199:0] $end
|
|
$var wire 2 Ch" rd_ptr_next_r [1:0] $end
|
|
$var wire 2 ;h" rd_ptr_r [1:0] $end
|
|
$var wire 2 3h" wr_ptr_r [1:0] $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope module s0_1_c0 $end
|
|
$var wire 32 #p" N [31:0] $end
|
|
$var wire 32 Wn" PASSTHRU [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 1 Io" flush $end
|
|
$var wire 243 O$! in [242:0] $end
|
|
$var wire 243 7Z" out [242:0] $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 1 %y stall $end
|
|
$var wire 243 7Z" value [242:0] $end
|
|
$upscope $end
|
|
$scope module snp_req_queue $end
|
|
$var wire 32 wn" BUFFERED_OUTPUT [31:0] $end
|
|
$var wire 32 io" DATAW [31:0] $end
|
|
$var wire 32 gn" SIZE [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 55 ;( data_in [54:0] $end
|
|
$var wire 55 9!! data_out [54:0] $end
|
|
$var wire 1 YC" empty $end
|
|
$var wire 1 aC" full $end
|
|
$var wire 1 Wv pop $end
|
|
$var wire 1 ?n" push $end
|
|
$var wire 1 I!! reading $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 5 #H" size [4:0] $end
|
|
$var wire 5 #H" size_r [4:0] $end
|
|
$var wire 1 K( writing $end
|
|
$scope module genblk3 $end
|
|
$var wire 55 +H" data(0) [54:0] $end
|
|
$var wire 55 -H" data(1) [54:0] $end
|
|
$var wire 55 ?H" data(10) [54:0] $end
|
|
$var wire 55 AH" data(11) [54:0] $end
|
|
$var wire 55 CH" data(12) [54:0] $end
|
|
$var wire 55 EH" data(13) [54:0] $end
|
|
$var wire 55 GH" data(14) [54:0] $end
|
|
$var wire 55 IH" data(15) [54:0] $end
|
|
$var wire 55 /H" data(2) [54:0] $end
|
|
$var wire 55 1H" data(3) [54:0] $end
|
|
$var wire 55 3H" data(4) [54:0] $end
|
|
$var wire 55 5H" data(5) [54:0] $end
|
|
$var wire 55 7H" data(6) [54:0] $end
|
|
$var wire 55 9H" data(7) [54:0] $end
|
|
$var wire 55 ;H" data(8) [54:0] $end
|
|
$var wire 55 =H" data(9) [54:0] $end
|
|
$scope module genblk2 $end
|
|
$var wire 1 IK" bypass_r $end
|
|
$var wire 55 !K" curr_r [54:0] $end
|
|
$var wire 1 YC" empty_r $end
|
|
$var wire 1 aC" full_r $end
|
|
$var wire 55 oJ" head_r [54:0] $end
|
|
$var wire 4 AK" rd_ptr_next_r [3:0] $end
|
|
$var wire 4 9K" rd_ptr_r [3:0] $end
|
|
$var wire 4 1K" wr_ptr_r [3:0] $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope module st_1e_2 $end
|
|
$var wire 32 3p" N [31:0] $end
|
|
$var wire 32 Wn" PASSTHRU [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 1 Io" flush $end
|
|
$var wire 316 Y)! in [315:0] $end
|
|
$var wire 316 y[" out [315:0] $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 1 %y stall $end
|
|
$var wire 316 y[" value [315:0] $end
|
|
$upscope $end
|
|
$scope module tag_data_access $end
|
|
$var wire 32 gn" BANK_LINE_SIZE [31:0] $end
|
|
$var wire 32 _n" CACHE_SIZE [31:0] $end
|
|
$var wire 32 wn" DRAM_ENABLE [31:0] $end
|
|
$var wire 32 on" NUM_BANKS [31:0] $end
|
|
$var wire 32 wn" STAGE_1_CYCLES [31:0] $end
|
|
$var wire 32 on" WORD_SIZE [31:0] $end
|
|
$var wire 32 wn" WRITE_ENABLE [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 128 M'! data_write [127:0] $end
|
|
$var wire 1 K| dirty_st1e $end
|
|
$var wire 16 S| dirtyb_st1e [15:0] $end
|
|
$var wire 1 %} fill_saw_dirty_st1e $end
|
|
$var wire 1 C| fill_sent $end
|
|
$var wire 1 W(! force_core_miss $end
|
|
$var wire 1 Sx force_request_miss_st1e $end
|
|
$var wire 1 m'! invalidate_line $end
|
|
$var wire 1 -} is_snp_st1e $end
|
|
$var wire 4 {| mem_byteen_st1e [3:0] $end
|
|
$var wire 1 s| mem_rw_st1e $end
|
|
$var wire 1 C| miss_st1e $end
|
|
$var wire 1 E} mrvq_init_ready_state_st1e $end
|
|
$var wire 128 s&! qual_read_data_st1 [127:0] $end
|
|
$var wire 1 [&! qual_read_dirty_st1 $end
|
|
$var wire 16 c&! qual_read_dirtyb_st1 [15:0] $end
|
|
$var wire 20 k&! qual_read_tag_st1 [19:0] $end
|
|
$var wire 1 S&! qual_read_valid_st1 $end
|
|
$var wire 128 3&! read_data_st1c(0) [127:0] $end
|
|
$var wire 1 y%! read_dirty_st1c(0) $end
|
|
$var wire 16 #&! read_dirtyb_st1c(0) [15:0] $end
|
|
$var wire 20 +&! read_tag_st1c(0) [19:0] $end
|
|
$var wire 1 q%! read_valid_st1c(0) $end
|
|
$var wire 6 1%! readaddr_st10 [5:0] $end
|
|
$var wire 128 y{ readdata_st1e [127:0] $end
|
|
$var wire 20 ;| readtag_st1e [19:0] $end
|
|
$var wire 32 q{ readword_st1e [31:0] $end
|
|
$var wire 1 O(! real_miss $end
|
|
$var wire 1 }'! real_writefill $end
|
|
$var wire 1 ?(! req_invalid $end
|
|
$var wire 1 G(! req_miss $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 1 7(! should_write $end
|
|
$var wire 1 m'! snoop_hit_no_pending $end
|
|
$var wire 1 5} snp_invalidate_st1e $end
|
|
$var wire 1 =} snp_to_mrvq_st1e $end
|
|
$var wire 1 %y stall $end
|
|
$var wire 1 %y stall_bank_pipe $end
|
|
$var wire 1 u'! tags_match $end
|
|
$var wire 128 y{ use_read_data_st1e [127:0] $end
|
|
$var wire 1 ='! use_read_dirty_st1e $end
|
|
$var wire 16 S| use_read_dirtyb_st1e [15:0] $end
|
|
$var wire 20 ;| use_read_tag_st1e [19:0] $end
|
|
$var wire 1 5'! use_read_valid_st1e $end
|
|
$var wire 128 M'! use_write_data [127:0] $end
|
|
$var wire 16 E'! use_write_enable [15:0] $end
|
|
$var wire 1 U} valid_req_st1e $end
|
|
$var wire 16 /(! we [15:0] $end
|
|
$var wire 2 i%! wordsel_st1e [1:0] $end
|
|
$var wire 26 m} writeaddr_st1e [25:0] $end
|
|
$var wire 128 I%! writedata_st1e [127:0] $end
|
|
$var wire 1 9%! writefill_st1e $end
|
|
$var wire 6 1%! writeladdr_st1e [5:0] $end
|
|
$var wire 20 '(! writetag_st1e [19:0] $end
|
|
$var wire 32 A%! writeword_st1e [31:0] $end
|
|
$scope module genblk4(0) $end
|
|
$var wire 1 _(! normal_write $end
|
|
$upscope $end
|
|
$scope module genblk4(1) $end
|
|
$var wire 1 g(! normal_write $end
|
|
$upscope $end
|
|
$scope module genblk4(2) $end
|
|
$var wire 1 o(! normal_write $end
|
|
$upscope $end
|
|
$scope module genblk4(3) $end
|
|
$var wire 1 w(! normal_write $end
|
|
$upscope $end
|
|
$scope module s0_1_c0 $end
|
|
$var wire 32 +p" N [31:0] $end
|
|
$var wire 32 wn" PASSTHRU [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 1 Io" flush $end
|
|
$var wire 166 ))! in [165:0] $end
|
|
$var wire 166 ))! out [165:0] $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 1 %y stall $end
|
|
$var wire 166 I[" value [165:0] $end
|
|
$upscope $end
|
|
$scope module tag_data_structure $end
|
|
$var wire 32 gn" BANK_LINE_SIZE [31:0] $end
|
|
$var wire 32 _n" CACHE_SIZE [31:0] $end
|
|
$var wire 32 on" NUM_BANKS [31:0] $end
|
|
$var wire 32 on" WORD_SIZE [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 64 wZ" dirty [63:0] $end
|
|
$var wire 1 !)! do_write $end
|
|
$var wire 1 C| fill_sent $end
|
|
$var wire 32 9[" i [31:0] $end
|
|
$var wire 1 m'! invalidate $end
|
|
$var wire 32 A[" j [31:0] $end
|
|
$var wire 6 1%! read_addr [5:0] $end
|
|
$var wire 128 s&! read_data [127:0] $end
|
|
$var wire 1 [&! read_dirty $end
|
|
$var wire 16 c&! read_dirtyb [15:0] $end
|
|
$var wire 20 k&! read_tag [19:0] $end
|
|
$var wire 1 S&! read_valid $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 1 %y stall_bank_pipe $end
|
|
$var wire 20 '(! tag_index [19:0] $end
|
|
$var wire 64 )[" valid [63:0] $end
|
|
$var wire 6 1%! write_addr [5:0] $end
|
|
$var wire 128 M'! write_data [127:0] $end
|
|
$var wire 16 E'! write_enable [15:0] $end
|
|
$var wire 1 }'! write_fill $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope module snp_rsp_arb $end
|
|
$var wire 32 gn" BANK_LINE_SIZE [31:0] $end
|
|
$var wire 32 on" NUM_BANKS [31:0] $end
|
|
$var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 2 c8 fsq_bank [1:0] $end
|
|
$var wire 1 k8 fsq_valid $end
|
|
$var wire 4 ; per_bank_snp_rsp_ready [3:0] $end
|
|
$var wire 112 A/ per_bank_snp_rsp_tag [111:0] $end
|
|
$var wire 4 9/ per_bank_snp_rsp_valid [3:0] $end
|
|
$var wire 1 [h" reset $end
|
|
$var wire 1 [l" snp_rsp_ready $end
|
|
$var wire 28 Sl" snp_rsp_tag [27:0] $end
|
|
$var wire 1 Kl" snp_rsp_valid $end
|
|
$scope module sel_ffsq $end
|
|
$var wire 32 on" N [31:0] $end
|
|
$var wire 1 Sh" clk $end
|
|
$var wire 2 c8 grant_index [1:0] $end
|
|
$var wire 4 s8 grant_onehot [3:0] $end
|
|
$var wire 1 k8 grant_valid $end
|
|
$var wire 4 9/ requests [3:0] $end
|
|
$var wire 1 [h" reset $end
|
|
$scope module genblk2 $end
|
|
$var wire 4 s8 grant_onehot_r [3:0] $end
|
|
$scope module priority_encoder $end
|
|
$var wire 32 on" N [31:0] $end
|
|
$var wire 4 9/ data_in [3:0] $end
|
|
$var wire 2 c8 data_out [1:0] $end
|
|
$var wire 32 {8 i [31:0] $end
|
|
$var wire 1 k8 valid_out $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$enddefinitions $end
|
|
|
|
|
|
#0
|
|
b0010000010000100 #
|
|
b0000 +
|
|
b0001 3
|
|
b0000 ;
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|
b0000 C
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|
0K
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|
1S
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|
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|
b0000 c
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
b0000100101001001100110000110101100001000011110000001100 /"
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|
0?"
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|
b1110001000001101100111000001101001001111011101101110101010110111111111100110110011011011010011011111001111001000011011001101001010111111001100110010011000 G"
|
|
0o"
|
|
b00000001010011001000101110011010100001000001100111011110111001000011100011101011000010000000111010101000011100110100110100101000111100101111100010010100010111111111111000100101001101010111100111100011110001100011100111101001111101001110100111010110100011100000010010111000100010100000101101101001001100010000001111 w"
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|
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b0000100101001001100110000110101100001000011110000001100 3$
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0C$
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b1110001000001101100111000001101001001111011101101110101010110111111111100110110011011011010011011111001111001000011011001101001010111111001100110010011000 K$
|
|
0s$
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|
b00000001010011001000101110011010100001000001100111011110111001000011100011101011000010000000111010101000011100110100110100101000111100101111100010010100010111111111111000100101001101010111100111100011110001100011100111101001111101001110100111010110100011100000010010111000100010100000101101101001001100010000001111 {$
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|
0m%
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|
b0000100101001001100110000110101100001000011110000001100 7&
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b1110001000001101100111000001101001001111011101101110101010110111111111100110110011011011010011011111001111001000011011001101001010111111001100110010011000 O&
|
|
0w&
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|
b00000001010011001000101110011010100001000001100111011110111001000011100011101011000010000000111010101000011100110100110100101000111100101111100010010100010111111111111000100101001101010111100111100011110001100011100111101001111101001110100111010110100011100000010010111000100010100000101101101001001100010000001111 !'
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|
0q'
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0y'
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0#(
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0+(
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|
03(
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|
b0000100101001001100110000110101100001000011110000001100 ;(
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|
0K(
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b1110001000001101100111000001101001001111011101101110101010110111111111100110110011011011010011011111001111001000011011001101001010111111001100110010011000 S(
|
|
0{(
|
|
b00000001010011001000101110011010100001000001100111011110111001000011100011101011000010000000111010101000011100110100110100101000111100101111100010010100010111111111111000100101001101010111100111100011110001100011100111101001111101001110100111010110100011100000010010111000100010100000101101101001001100010000001111 %)
|
|
0u)
|
|
0})
|
|
0'*
|
|
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|
|
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|
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
|
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|
|
b1110 Y+
|
|
b0110 a+
|
|
b01111000 i+
|
|
b11100100000010111111001111110000010011001000100111100001111100001000100100001001000000101011110100100101010110111000011111110100 q+
|
|
b101001110001100111111110010110011110110001010100001110111101110001000111010010101100111100110010110100000011100011101011010010000111000101111011101101101100111010011000 3,
|
|
b0000 c,
|
|
b1011100010010101010101010011111111011011110101101011001000100111011101110000100101010100110111101001101001001100 k,
|
|
b1110 --
|
|
b0000 5-
|
|
b1110011000011101110001111110010101101111001011011000011110000110 =-
|
|
b1010000110111000110010001111101101111010110100010110101011111111111111101111100001011111100101000111101011110100 M-
|
|
b11010100101101101101000010001101000110000100000010001010101010001100100011001010100010011000101011000011010100111010001100101010001000111001100101110000010001101011101010011111111011111011000010001010000111011100101001110010001001100100010100111010000111110000101010100111100011100010001000110010011100110110010111110011110010100100111010001011110011100001000000111100001111111010111000010111101100001100011010000110100010001000011011101101111111100001001000100011001111011011101001111011011111000110011000100111 m-
|
|
b1000 1/
|
|
b1000 9/
|
|
b1011000100111100111100010011001010111001001101100111010111100001100100000111011000011100110111001111101011001110 A/
|
|
b00 a/
|
|
b00100101010110111000011111110100 i/
|
|
b000111000101111011101101101100111010011000 q/
|
|
0#0
|
|
0+0
|
|
b1000011110000110 30
|
|
b11111001010001111010111101 ;0
|
|
b00010111101100001100011010000110100010001000011011101101111111100001001000100011001111011011101001111011011111000110011000100111 C0
|
|
0c0
|
|
b1100110111001111101011001110 k0
|
|
b10 s0
|
|
b10001001000010010000001010111101 {0
|
|
b111100110010110100000011100011101011010010 %1
|
|
051
|
|
0=1
|
|
b0110111100101101 E1
|
|
b11111111111111101111100001 M1
|
|
b00001010101001111000111000100010001100100111001101100101111100111100101001001110100010111100111000010000001111000011111110101110 U1
|
|
0u1
|
|
b1110000110010000011101100001 }1
|
|
b11 '2
|
|
b01001100100010011110000111110000 /2
|
|
b010100001110111101110001000111010010101100 72
|
|
0G2
|
|
0O2
|
|
b1100011111100101 W2
|
|
b10110111101011010001011010 _2
|
|
b00100011100110010111000001000110101110101001111111101111101100001000101000011101110010100111001000100110010001010011101000011111 g2
|
|
0)3
|
|
b0010101110010011011001110101 13
|
|
b01 93
|
|
b11100100000010111111001111110000 A3
|
|
b101001110001100111111110010110011110110001 I3
|
|
0Y3
|
|
0a3
|
|
b1110011000011101 i3
|
|
b10100001101110001100100011 q3
|
|
b11010100101101101101000010001101000110000100000010001010101010001100100011001010100010011000101011000011010100111010001100101010 y3
|
|
1;4
|
|
b1011000100111100111100010011 C4
|
|
0K4
|
|
1S4
|
|
b0100010111010000000000100001 [4
|
|
0c4
|
|
0k4
|
|
b00 s4
|
|
0{4
|
|
0%5
|
|
1-5
|
|
b0000 55
|
|
b1010100101100111001010000011011011000110110111111110101100110100010000101010111101000011001001100110111101001110 =5
|
|
b0100 ]5
|
|
b1111010010110011011110110111010001011101000000000010000110010101101001001111110000000110100110111010111000110110 e5
|
|
b0000 '6
|
|
1/6
|
|
076
|
|
b10 ?6
|
|
1G6
|
|
b00001011100010010101010101010011111111011011110101101011001000100111011101110000100101010100110111101001101001001100 O6
|
|
b00001010100101100111001010000011011011000110110111111110101100110100010000101010111101000011001001100110111101001110 o6
|
|
017
|
|
b0100 97
|
|
b11111111111111111111111111111111 A7
|
|
b0001 I7
|
|
b11111111111111111111111111111111 Q7
|
|
b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Y7
|
|
b000111000101111011101101101100111010011000 y7
|
|
b00 +8
|
|
b0000 38
|
|
b0001 ;8
|
|
1C8
|
|
b0010 K8
|
|
b0010 S8
|
|
b11111111111111111111111111111111 [8
|
|
b11 c8
|
|
1k8
|
|
b1000 s8
|
|
b11111111111111111111111111111111 {8
|
|
0%9
|
|
b01000110101101101001001010 -9
|
|
159
|
|
b1110111111101011000111000001 =9
|
|
0E9
|
|
b01110010110011111100100111 M9
|
|
b10110011000111101100011111000101110010101100101101000110010010000001010011001101101011000100010010010110011000101011110001111100 U9
|
|
0u9
|
|
1}9
|
|
0':
|
|
b00 /:
|
|
17:
|
|
b1010 ?:
|
|
b001001010010011111001000111111 G:
|
|
b10011101000011000111111001100100 O:
|
|
0W:
|
|
0_:
|
|
0g:
|
|
0o:
|
|
0w:
|
|
0!;
|
|
0);
|
|
01;
|
|
09;
|
|
0A;
|
|
1I;
|
|
1Q;
|
|
1Y;
|
|
1a;
|
|
1i;
|
|
0q;
|
|
0y;
|
|
0#<
|
|
0+<
|
|
b00000000000000000000000000 3<
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b110 eS!
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b01101110101101100001000011111110010100111111010110101011111101001100101011110001000101001111111101000010101001100110111110101011010001110111000111001000110001010100101101000111000100010010010000110110 mS!
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b00010000101011111110101011100010111100011011110001001011001010000100110110000111000101000010001101000000100100010010001011001001000001100110000000101010001000010111101010111010110110001110100111100101 tS!
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b10101010101111001011101101011101110011111001111111101011001000101111101100001110000010111000011001011000111000100010010001010000101011100110101010111000011100011100010010011010110010110110010001110111 {S!
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b00000100011100010000001101110101000010010000010111110111110001110110100010111000001100101011001110011111010110001100000010111000001011010100010111011100001000110010100010110011001101111111000110010010 $T!
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b00100001111000011011111001010001111010111101000101111011000011000110100001101000100010000110111011011111111000010010001000110011110110111010011110110111110001100110001001111100110111001111101011001110 3V!
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b00000101001111110101111110010101110110000001010011000101010001000110100000101100101000101111010010011000111000110010111100011100100001110010010010110010101011001010001110010100010001110000000100000011 kV!
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b11 EW!
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b00 MW!
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b10 UW!
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1mW!
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0'X!
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b101111100100000011000111101101011011001010 /X!
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0?X!
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1GX!
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b01 OX!
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b10001000001000111101000011 WX!
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b01 _X!
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b01000110000001111100001101100001 gX!
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b101100101101100000111010111010010001000100 oX!
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b1011 !Y!
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01Y!
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b11 9Y!
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b011001011010101111001010001100111000110111 AY!
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0QY!
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b0111 YY!
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1aY!
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1iY!
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b10 qY!
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b11100110000011010011010000101101 yY!
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b11010101000011010111011010110011 #Z!
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b11000111100111110001000110100110011011111001000111111010110100110101101001111100100100101001010100010100100000110001010010010111 +Z!
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0KZ!
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0SZ!
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b1100100001101110 [Z!
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b0110010110101011110010100011001110001101110011111 cZ!
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b00011111010101111011 sZ!
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b1111001010001100111000110111 }[!
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b1011010001011111111101110011101000000110110010111101100 9\!
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b0011111111001101110101011111001100000110110101001001011 ;\!
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b1010000011010101101100101110100110000101110001101000010 =\!
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b0010000110110010110111010011111100111011110001100110111 ?\!
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b0110010101110111101101011000110011000000111001000010100 A\!
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b1100100011101101100111000111010111011000000011111110010 C\!
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b1101011011101011100001010011011010100100000000010001010 E\!
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b1111100111010001001000001011011010010001011010110011000 G\!
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b0000001010100010010000001000101011101001010001100010011 I\!
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b1111001101100010101001001111101001101111100111011110100 K\!
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b1110011001101110100100000110010111110000100000100110111 M\!
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b1011111001100100011101110010101101101111010011010000010 O\!
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b0001100001100001001000110010000010101000001101101110000 Q\!
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b0001100001011010101101000011011001001100110010010010010 S\!
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b1000111000000011011101000010110110110010111100001010011 U\!
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b1011111010000010110011000101111100001011100010011111010 {^!
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b0000100100101111101110101101111001111101110100101110010 -_!
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b1110011010001111011010011000001100000101100001110000100100000011101010011011011101111001110110001001101010000011011011111110110010100110011101111111111110 e_!
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b0001011000001100100110100000111110100000101101000111110110101000111001001100110101001000110100010111111101111011111111000101011011010011011100100100011101 j_!
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b0010001101010101111010111111010011001100100001101110101010010100001110101010111011011000111011111100111011110011000001011100100111010111001111000101010000 o_!
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b1111111001110001101011011101011110001101011000011000010010010011001011111111011101100111001011000011111011001101000011100111110101100010101000101110100111 t_!
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b1110011010010100001010110100100010000111011011001001011001001001001100001001110000100110101011111110110110010010111010100101011100100000000101000001001111 y_!
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b1110101101111001000001101010010111101010110010111100100110000000011101111011110101011110100001110010111101001000100101100101010110110001001000011110110110 ~_!
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b1111001100111001100011100111101100011110101111111001010000101011010110000011011001001101001011101110000011101101110110101101011100001011100001101100001101 %`!
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b1111011011010110111000000100100111010101010010010001001110001011110011100000110101111010000010110110011001110110101101101110011010001010000101000101011111 *`!
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b1010001101100000110111101111000111010101011101000010110001001101100011111110101110000110000001111011010011000110000101111010011101011011000110011111000110 /`!
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b1111111110001100110011111011001010101001111100100100010100110101000110100100011000010011010011111100010111100001000010011101111001110110001101100110111111 4`!
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b0010011000111101101110100001111011000101001011001110000111100110010110100000000110101001110001111101001001010101101100001111011110111000000111000100001110 9`!
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b1110001000100010001010100100101001100111110001000010111111101101110111000100001011100000101100011111010110001100000101111001010000010010011101011000011001 >`!
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b1101000111111111001111100011001011110011111111101010000110110010101111101001110101000110101100011001100011000001000001010110110010010100001010101100001010 C`!
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b1100101100011010100010100011111100111001101100011000101101011101010101000111000000000110000000011101001101010010011111110110100010001011100101001011100111 H`!
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b1010101001111010101101100101100011110000001011001000001001101110010011101001110111101000010101111110011111110011100110101001000011010000101100100100111101 M`!
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b0001010111010000010110110101100111001101011101110000110011000111100000111011110011101110010010001100100110010000001010110111111101000110011011110000001101 R`!
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b1100101111011110100110001110011111001010100110111000110001110011000001011010000111101110101101100111011000111011000011000001010010001000010011110000011000 Sf!
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b0111011001101101010001000101011101101011001110000000011111111110101101011110001000010000011110010001001000100001101011000110101100011100110010010000010111 {f!
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b0011 Eg!
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b1100 Mg!
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b1000 Ug!
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0]g!
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b1010 eg!
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b0101 mg!
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b0110100001011011 ug!
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b101110111000010110001111110000010101111101001001011100001000101100000010100101100110000101011101111100100001000001110110 }g!
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b10001100011100111110110001100110101101100100001010001001101001010111011001001101001010011111110111001111100101100000010010100100 ?h!
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1_h!
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0gh!
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b010 oh!
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b10100110011001100101000111000110001111110011001110001111011001010101100111101101000000010111000100101110100011011000001011001101100111111101110100000100001100011001010100100111110001111101101000100110110100100011011000001101011011100101100111011110010000110100001010011001001011110000001000110011010010000011100100 wh!
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b10101000001011001010110000001101001101011010101000111110110000010001000100001100111010110101101111110100110011000001000010101111101011011011111110010100101011001010110100001010001000011100101001010100001110100101010110011101101101001101011000000100101001110010101110001011100110001000101110000111100010100110100001 #i!
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b00100100000010010110000110000001110000100000000001110011011001111010101101100001000110111010100101110101001111101110010010011011101010000011001000010010110100001001110100011101001111010111001111101111101110100010100011110110010000110000001000000001101101001010001101010011110011111110000010110011111110101000001101 -i!
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b10100111111001010001101001001010110110010101010101010000011111100010000001001001110000001101011010011111100000001000111000110101010000000111110011110111101010100000010001100010101011100110100001011010000111101001000111011100101011011011100110000110111100011111001111001010010000111101010101100101101101000111001010 7i!
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b00111100000111101111000010001010101111000110001010001010101011000101010100001101100001110001111110111001110001111110111000011010101010011110000101100111010010100000111100110110110000011110010001110010001110110111110110100101000010000110100001110110111011110011101010001000010001011001010000100110000111000001000110 ?l!
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b10011100110100000011110101000000100011000000011110000110111111100111101100010001011101100110101100011100011101100001111111000111000001110001100111011000101101010000101100101010000010000000010100010000111011101100010011111000000010000100011111010001011000111001001000110111011010001101101010001110001111110111000000 1m!
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b01 #n!
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b10 +n!
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b01 3n!
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1;n!
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b000100110110011001011100111110011110101101111101010100011001111010010100101100010011110000001111111001101100100001100001011100101111111000000000100001101010111100001010011010010001001011111011000100000100110101000101000110111111101110100000100 Cn!
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b0100001001110101011000100010110110011001011100111010010011001110 %o!
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b1100010110001000100111100011010101111011110000001011011011100000 5o!
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b00000101101111100101111001111100 Eo!
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b10001001111111111000011110100010 Mo!
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b1100010111000000010000100001000110100000100100011000101111110000110011111110010011011011001111000010011001101101011010001011100101011101001110100010100001000010111011 Uo!
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b1110010110010011101110111000010010110111001100000110100110100001011011101010100001101011101101011001111000111100111110001000110100110011011111001000111111010110100110101101001111100100100101001010100010100100000110001010010010111000111110101011110110011001000011011100110010110101011110010100011001110001101110011111 'p!
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b1011101101111010000100001011101100011001101010111001100010111100011001001110001010101 wp!
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b0001000100111101000100111010001101100111100010101111101010001000001000001101110111101 zp!
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b1110000000101110010100001111100000010111011111101010000011110001111000000001101100100 }p!
|
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b1001000011010100111100111001000110011001110011010011111010100111011011110010111100011 "q!
|
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b0010001100011111110001011011001000001111111001010100011010110011110001011011110101101 %q!
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b0111110111110000011011110001111001011011101011110111011000001010000111101010001011001 (q!
|
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b0100011000000111110000110110000101101100101101100000111010111010010001000100010110100 +q!
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b0110110011111100101101110010101011010011010010110011000101010011010110001011101110000 .q!
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b1111100000010011101000101001100101000011101101110000101001010101110110011010011111001 1q!
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b0001111001110001000001110011010011101011101110110111111001100100000110010100111110111 4q!
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b1000000000101111011110001111000010100011001001111101110101111011011010001100000100101 7q!
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b1001001101000011100110000011001001111110111000011010001010100101110100010001100000001 :q!
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b0011100111100010000000011100111110100010100101111101101000111010011111011110101100111 =q!
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b0100010101010101100011100000100101001001010100000100011101101100100111000101110111001 @q!
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b1001000111001110001110100100001010011100000000110011111110011010110000101101010111010 Cq!
|
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b1101111011100100001000110001111110001000100011001100101000111110000110100100111001011 Fq!
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b00010111010100011110100001110101000110101010111011101101010011110001110110010100100010011011000111111111011001110011001000000111010000001111110010100100010101001111010110011100000000010000000100111010110101010100001110110100010110000010001000001000111101000011000110010010110010100101100101010001001000110000010011101000011110101010010001100011110001011110001100010110110011101011110101001000100011010101001100111110 !u!
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b1100100001100011 +v!
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b0010101111000000 3v!
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b0110 ;v!
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b1110 Cv!
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b0001 Kv!
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b11011 Sv!
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1[v!
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b011 cv!
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b0001010110101001010100010001111101111100110011110100111001010111001011100000 kv!
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b0100110111101111011101100100010001011100000000111001100010000000100010101110 nv!
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b1010100110000101111011011001100001010001101000011100100110010111101000100101 qv!
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b0100111001011110010001100100110100100001110100100100000100010110001011010101 tv!
|
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b0110001010101011011100111101011111011101100010111000110110011101010111110010 mw!
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b1011110011001011010000001110001110101101001010001001000010010000001010111101 'x!
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b11 ?x!
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b00 Gx!
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b01 Ox!
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b101 _x!
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b10000001100010100001110001111011010001000011010001101110100111000101110010011000111001010000110111101001111110001110000101100001111100011011111011100001101110101001100000101100001110011111111010001010 gx!
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b01111001001100011010111110100100111010110011110110011101110111100000101100111111110010000000101111110101111101000011110101000100101100101100111000011110011010100101100111100110100100111000100111110010 nx!
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|
b00101010101110011111100001011011011111111011000011111011000110111111011000111101110000011110100100100100010100101111001001001000110101000111011000101000001111110000101101011101010000111010011001101101 ux!
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|
b00111100000010001000001101111001000010010000110100001010111100011011100010011100000001010000011100011010011111110010100000011010001101100101111111000000100001101010100110100001110011110101101100001100 |x!
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|
b00011011110010110111111111111111101111100001000010101010011110001110001000100011001001110011011001011111001111001010010011101000101111001110000100000011110000111111101011101110000110010000011101100001 -{!
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b01100101010010011001010110010100000110001000111100110000110110011101000000101011001101010101111101110110100010111110010001101011000000011111111111111001000100010010101011001100101111011100110001100010 e{!
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b10101011011001010001100001 Q}!
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b10 Y}!
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b101100110101001100110101110110000101111000 i}!
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b0001 y}!
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b010100100010000010010011111010110110000110 ;~!
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b00111111101011011001010000111110 s~!
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b10001110100001101111101111101111 {~!
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b01011010000001100100010001110010011001100011000000011000011100100100011001110111001011111111100001111110010111100100000010110111 %!"
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0E!"
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b1001111010010001 U!"
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b0101001000100000100100111110101101100001100001010 ]!"
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b11010011010010000011 m!"
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b0010010011111010110110000110 w""
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b01000 )#"
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b1110000000111001001000110111010001101011101110111101001 1#"
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b0001010001100111101110111011011000110001110001110001110 3#"
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b0000001111111011101100001000000110100000101110010010010 5#"
|
|
b1011001000010010001111000010010001110110101010100100010 7#"
|
|
b0101000011110100010100101011100001010111110101011011110 9#"
|
|
b1011011101010100100010010101001010110110001111010010100 ;#"
|
|
b1010010110001111100000100101101111111100010111100000000 =#"
|
|
b1000101101111011011101001110000010111010101111101010100 ?#"
|
|
b0100011101010000101010101001010101111010001011011010111 A#"
|
|
b1101001111110110011111101110111110010100001111100011100 C#"
|
|
b0001110001010100100011011111000000111010110001011011110 E#"
|
|
b0011111110011111101101100010100101110011001010110101010 G#"
|
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b0101011100101010101110001100100010000000111110110000001 I#"
|
|
b0100110101100101000101000101111011111000011100101111011 K#"
|
|
b1011110001100001111100010010111001001101110110100011110 M#"
|
|
b1011001011110001011100111001011010110001000011101011011 O#"
|
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b0010101111010001100101000110111100011101101110010111000 u%"
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b1011011111000000101111111110011000100000000110010010000 '&"
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b0011110011110011000110100111101110101101101000111100100010011110101001011101111110101011011111000100000000001101010100011100010101011010011111000110001001 _&"
|
|
b0011001110000010100011111000001001111000111101100100111101000100111110001000100011101101100110000110011010111101110100010010001101001100010111101110011100 d&"
|
|
b0000100011010010100010011010001001001101100110010011001010100101000101101111111010001111001111011001010110101010001010011010010000011111000001111110111100 i&"
|
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b0110001111001110100111000101011100100000001000010110001101011111100101010101000100100011010101000010100011101010000011100000010101111011111000110101111001 n&"
|
|
b1010001001111111001000101010101111110100111000101010110111000001100101011111111000010111001000001000110010110001111011001000100101100001000101001111000100 s&"
|
|
b1000101110100010010110100001110000010100101101010110111101010100010001011010110000000010011100100001000110111100011100111010111011111110100111100100111100 x&"
|
|
b0000100001010100101101110111100011101011100010111011100110011111010011001011111010110101011101101100000011011101100110001010101101101000000101010101100000 }&"
|
|
b0000110101011000110100110101110010000000011110011100101001101100101101010101101110100111110111000010011000010011110000111001110000010001111001001110100111 $'"
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b1010110100011001101011111100001000110000100111001100001000110101111110110011010000110110011100011101001011100111100001100100001010100110010100001100101111 )'"
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b1010100010000011100101000001010000111001000101111100101101110000001100110111000100011101010111100000110011101101110101110001110100010010100010101110011001 .'"
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b0011110100101111101100101100011011000111110010100011000011010100000110110100100110000010001110101000111001101100010111101001100100010110000101010000111110 3'"
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b0001100110000100110000111101001100110001110010111000100000011100000011101100000111110110111010100110001000010111110001000000101000110000000110001001101100 8'"
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b1001111001110111100001100100101001111110011100110101011001010001001110110101100110100110110100101111010010110001101000101110101010000010110111011110101101 ='"
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|
b1110000000010000011000001111111111011111111101001101110101010100000001011010000101001111011110011001101011100000111011001001110011111100000011011101010110 B'"
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|
b0011110101010001100111011010001000010001010101101011010011011110011110010111101011101010011000101001101010110101001010011010011010110000011110000010111010 G'"
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|
b0001000101101011000010101111100100001101111100101111110110110101011101000001101001010110010000111110001100101000000001111110110111101110110110100110111111 L'"
|
|
b0101110001111111011011110001100110010110001011100100000100011100100110011110111101001011001101111010000110011001110100101100100011001011000010111000101110 M-"
|
|
b0111010110100011001010111110011010011000010000101001111100000110100100000001110010111100000101001000111001010100101010110100101101001111001000011000001001 u-"
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b1111 ?."
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b111011001011110001010100011011001011001000001111000001110000010101101101110001101100101111111011011110010000010100110000 w."
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b00100101010010001101110101100100101110001001000110101110001011110011001010110010101001101000101100000101001111101010110110000000 9/"
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b01000000100010101010000010110110100000111110110101000011010011110000111001010010010101101110001001101011001101110101110010001010011000111001001000111010100111011010010100101011111010110001000010011011001011010110111111100000001000100001110011010010011001010100001110101101011111111100010010100011101110011100001010 q/"
|
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b00000101100101010011001110000000110101001011111101001100011000000010100011011010000100001001100111011011110000011110100101110100101001000000101110110111110010110011111001000000101100010010111101101011010111100011110000000110101111001000100011000001101011111110111101100100100100101110000011011111011110000011101010 {/"
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b11101111100101010001101010010011100111100100010010010110111110101000111001110110010011100100110101101101010101001010001111110010100011010001111000010101000000101000101000110111010011011101110001101001001111001000010010101111001011110101110100110110100000010010011100000011000110110100110001100011010100101101101111 '0"
|
|
b01110011101011001000100011100011101001000010000100100110011101000010111110100000011001011000000001100101101011011110010001000001000110000100100000000100111100000110100101111001011001111111011000000101001111110010100001000010110011100011010001100111110110100011111000010001101001101101110101111010110001111001010111 10"
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|
b00011000100000010110100011011011101011100100100111000011111101001011111101111011010010010011101100011111011101001010010000111111110000110011011000001101011011010010011110110011010101111100011001110001000011011011001001111011101001100100011101100001010101011000000000001110110110011010111001011000000101011111010001 93"
|
|
b00111001101001011001111111110100111100111000010011000110110101000101100010111001111101101110011110001010100111001011011100000110111101010101111100001010101010000010001000100100000111011111010000001001110101110001010110101000010111011001000000110011100010000001010000001010100010001010000010011100010111101001000010 +4"
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b00 {4"
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b110101101010110100111110110010011011111100010001000001001001001000100101000100101001110110100001010100101010111010000001001100000110101111000100011000100001011100101100100111001110100111000000110100001110001101001111110011001110100110011110011 =5"
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b0111110110001101111000101100111101110111100100001000111110110100 }5"
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b0100010000100111100001011101001111110111110110100011110111110101 /6"
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b11111001001101101100000010101010 ?6"
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b00001001111100011111110001011101 G6"
|
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b1101101101110110000100110101100011101010001010100011011000111101111100000000101011100000010000100011111011010100100010100111000000101110100100101001100100011011111111 O6"
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b1110011101111110110111101011010110011001111111010110110010100001111101000111010000110111110111110111101011010000001100100010001110010011001100011000000011000011100100100011001110111001011111111100001111110010111100100000010110111110100110100100000110010011110100100010101001000100000100100111110101101100001100001010 !7"
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b1010110000101101001110111001001101111111101100101111001100101111011101110111111110001 q7"
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b0010011001001000010011011000011101011111100100010010101000100110100100000101001101001 t7"
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b0011110001101000000111111011010101110000101011011111100010010001000010110010101000110 w7"
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b1001110110011001101000101110110011011011010001100111010010101010010111000000000001000 z7"
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b1110010110101001001001000000101101101100110101001100110101110110000101111000100011001 }7"
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b1001001100101101111001101110011000110101111100011001000010010001001001011101001110111 "8"
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b0101000111001101101001010000001101011111011101111110010101001010010000111010011000101 %8"
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b1011011001111110000111000001010010010001000010010011101000100101100010000011010111011 (8"
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b1001010110110110000100110011101110000100101100010101111110010100100011111111001000101 +8"
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b1011000111011001001001011001011001101101101111101010000000010111000011110100001000100 .8"
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b0011011100001011011011011111001010111101111000101001100010000101111010101110101111010 18"
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b1000101101011010100100101100011000101001001000010111110010011001000011111101000110100 48"
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b1110101110100111111011111101011101111110101100100000001111111010110111101111110101000 78"
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b1011001100010110110101101000011100001101001011110100111100011001010101000011111011000 :8"
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b1000001011110011010011111011001000001101000101110011101100100100110101101110101100110 =8"
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b1110011010111110010000111011010011111101101000001011111111111111010111101101001111001 @8"
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b00110111101111001110100101110101010110001010010110101000000001100100001010111101010011111000110011101111101000010100100111000000001101000001011001011000101100110110100010111000100101110100010001001111000011011110100101010110001010100101000101110001101110010001011011010111111010110110101010101101100101000110000100000000011100101001010100001111011010111010001101111111010011101110010000000110010011110100000111000010 y;"
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b1011100000000100111111000011001101011101110010000101000000010000111110101011 h="
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b1000000101111011100010011011010001001001111010111101010100001000111011111111 k="
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b1101110101100001000111000111010001010110110101101010011110110101111110011011 n="
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b0010110100000110100101001011010000000111010011111010010010101010001111010101 g>"
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b1101010000111011110111000100011101001010110001001100100010011110000111110000 !?"
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b10110101010100101010000001001101111000010001101101100000011010001100101010100010001100110111111001010000110001101110111001011100011011001001100101001000000011010110110001001010010010001110110000101110 h?"
|
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b01000111101011101111010011001100010101010001010101010010001110100001111010001010111001111101000110011011001011000100101001000101001100011011100101000010001101100101110011111110010100101001101110000011 o?"
|
|
b10100011010101011010011011001101001101000111101010011001110010101100000101011100011000100101010000111010000010011110001000110101101100011001001100111011011111000100101110101111100010110000001101010000 v?"
|
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b01011000101010100011010000001111001011100111100011101101000111110101011010010100110101101101110010111100100001000111101001101101001011001001100010110101111011001000001100101111010100111101110011000001 'B"
|
|
b00110001111110010110110111101011010001011010001000111001100101110000010001101011101010011111111011111011000010001010000111011100101001110010001001100100010100111010000111110010101110010011011001110101 _B"
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b00 9C"
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b01000000010111110110101001111001001011110101010011000001110101110000011100101011110111011110101100111101001111110100011010111101 }E"
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b0111101000011101000101001110111111111110111010111 WF"
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b1010010000110000000101110111010100111110000101001110111 +H"
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b1001111110010110000011001000110010111100000000001101111 -H"
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b1011110101111111111011000101000111101010110100110101001 /H"
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b0010101110101100001000110101001110101111100100010011001 1H"
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b1001010000010100110111011101001110001110000100001000010 3H"
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b1101000000100110100101101011101111011110101011111111010 5H"
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b1110110001001011001110001001000011010010011110010000100 7H"
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b1100111010001010001011111101011110111101101111101111001 9H"
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b1111010010000011110110011001111010110110010100100011111 ;H"
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b1100110010000100011010001000010001101101001010000111001 =H"
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b0010100101111010100000110011101010100011101011000111101 ?H"
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b0111011010011100000010011101011110011111000101010111101 AH"
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b1101000110011011000100100110101101010010100010011011100 CH"
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b0011010100000001011010100101001000111010110011111111101 EH"
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b1000110110001100001101101000001001011110011101000100110 GH"
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b0100111000001111101010101000001011011100101111111000110 IH"
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b0010011010101111101111100001001100100100101011111010010 oJ"
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b0000100001000001111010111010100000001111011001111101101 !K"
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b0110101000111111011110110000101000000111110011110010010000100001011110110101001001000001101010010100001001011101110111001100001101111100010110101010011000 YK"
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b1110010101100100101000000011111111110001010100101110101100000001010100010000100111110101011011100110001001110110101101101000011111001001110101100000001111 ^K"
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b1001010111111100111011000001100000011011100000000101100001110111111000010001000110101110111011010010001101001101000100111011100110110111101011111010100101 cK"
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b0100101011011100100010011011000110101000101100110110100010011101000111001010111100110111001111110011100101010111100100110101011011001111000101110100110110 hK"
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b0110101001101011010100111000111110000110111110111101000000110101101000100000101100110011101000010111100011101011100100000001101011001100110100111111001000 mK"
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b1001000110000110101100011000011011111111110011011101101011111100101001100110101010001111110010011011000001100010010111110111111111110111110010011011000111 rK"
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|
b1100011010100001010000101100011010011000101101101100101000001100011101000001100111110000000000101100110100001000111011000110011010111010010100110010111011 wK"
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b1100110110001110111001001111011100111111010011011011000100101100100100010101110011100011101001111001111011000011110001110000011100000101001001110111110111 |K"
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b0011000111010010110001111000110110011011100011100011101110110011100111101100000000100101111000001111100111010000101111101101100000111110100010011010001000 #L"
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b1010100011100000011001000100010111101011001110000001010001010011010101011001100000101001001011011110010001001111111110101110011011100001100001101000111100 (L"
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b0000001110110001011001000100100001100100101000111011100011101001110011101010000000010001101110000100011110010101111001000010001111010101110001111000000111 -L"
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b0111111101111110110010011000111000110101000010001001010110001110011001100101100110010011100011011000010100110000011010101000011111001101100110101011001011 2L"
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b0001100100101011100000011110110111011111100111001000100110011100100010100110101111001100011001010100110101111101011100011100111111100110110101000011011110 7L"
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b0001111001011001011100001101000011100011010010111100110100111000110001001010000111000101010100110100000100111100010010001100110001000100101011111110011011 <L"
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b1100011111010111001011111010011001101100111000111011101110010100100010100100011011110001100010000010101001101011101110111100001011011000100011100101010011 AL"
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b1010011000011010010011011000010110010001111100001000101100010100010101001000010101000110000101010010011100110000100111000010000111001011000110100111011110 FL"
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b0001111010101100111100011000001111011110001110110101010100001011111001011111011101000011101111001000111110111000100110101101101111000011100111111111000101 GR"
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b1001001101010001110110111101001111001000011011111001001011011000000011111100010111010110111011101001100100100100000010100000011000011101101100000100011000 oR"
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b01010110111001000011100111101111100001101101001110110000011001000101100011011011100101001000101110000100000101101110000110110100 3T"
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b10000001010000001101101110100100010011000111000010011000110111000111001011101101001001000010011011001111111110100010010111111010101110001000111000101111101110100010110111001100001000100010011011000110110111011101001010101011010011101001000101010111000000110110100101000110101100101100011111000010010011000111110001 kT"
|
|
b10011111011101100011110000011011110011110101101011000011000000011100100000001111000001110001011111111001001010111011011000000111010111001101110111111010010100011001111001100110100110001001011010101111100101011110000001101101000000011100010010001010111000100000110010100010011001010010000110101101100101001010110000 uT"
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b01111101111000011000111111100010000011101110111010010111110011101110011110100011111101011010011111010011110011010110000001100111001011000001110111111110101111000100101111111010100001110010011110101011100100101010000101111110111001010101100001110010110001010001001000000000011000001110010100010001100011000011010010 !U"
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b10111001110001010111010011100111101010101100001101010010010110000100110001110011111100010011000110101000011111111011110100010000000010010010110100011111010010010010110100000011010011000111110010111101101000000000111100010001110010011010110000101101101100011011101000011001110000011000011110100101100111001000110110 +U"
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b11110101100001010111010001110111101101011111100110011011101101110101101110100011000010010001011001110011100111010100000111010010111101101101101000110011001001001110111101000010010111010010101101000011001001100010000010000001111101110101111001000000011010001100000011110100000111000110101001010010111100010000100100 3X"
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|
b10010111101100000011111001000110000001000101110001111110111000000101011011010100111100110100000011101011001100010101010100011001100111000011100101011000001010001110001001110011100011100111100000100101100101101011001111111110010110110011010100010101101100111000100111100001000001111011110011101010010101100111110101 %Y"
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b001001111111011111000011010010000100110001001011010001111100000100011111101001010010010001000101000001001000011111001111000001110100111011011000000000000001100000101100100011010110011100101010111001100111111010111010000111011101100100011011011 7Z"
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b1010101110001100000110011011101101000001000111101101110110011111 wZ"
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b1101100100101111100010101110011111100110001010101100000100100000 )["
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b10111001111100001101011000000010 9["
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b10110001011101010110010110100100 A["
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b0011100101110110000011101100000101110011110000010100101111111000100001110111011000001101111100110011100011101110001110110000111101111110101010101110100000001010000010 I["
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b1010000111011100010010101010101010001000110000111101101000101011010100100101010110101000001110010010101000000010111110110101001111001001011110101010011000001110101110000011100101011110111011110101100111101001111110100011010111101010001110111101110100100001001011001000111101000011101000101001110111111111110111010111 y["
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b1011110101101111100111010011011011100110101000010110101110001111101110111110101010100 k\"
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b1101000010101011111100011010010101000111100100100001011000010001011111110011011001110 z\"
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b0111000011000000000100001001000001111000011011111000011101010010110000101100000001011 }\"
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b1111111100111001111101000010010111011000101110011000111000111001010101001011011100100 "]"
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b1000111010011100010000101101110111100001001111001011110000001011101111011001010000011 %]"
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b0100110100010100001111111001100010011101101101101001111011111111011010010111101000100 (]"
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b0101101100100011100100101111011100010001001110011110000000101101101100001110000111101 +]"
|
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b1011100100011100001011100010111010110110111111001000011110000101101010010011010011011 .]"
|
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b0101100111001100100000000101001011110010001010100001111000100011110011001000010110011 1]"
|
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b1000101101011001001111011011001101101011000000100101010011001010001001111100001011110 4]"
|
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b0001010000010001111110001100110001010011111001110110110001010000010110010101001011010 7]"
|
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b0011100001101101111010101000110011100111100100001110110101001001000010101111001010001 :]"
|
|
b01100011010000101100101100010100010100101101111010000011010010101001001000011010010011111100000101111110110010000010011010001000010010001011000011100111111101101100001011110111001001101100101001100001101100010101001001010111100011100010001110011000101010101100111000110111010000010011000100010111100010011011110010001011000011001010011001111010101010101100010000101011110100110011011110001101100101101111101101101000 s`"
|
|
b0011001010110010 }a"
|
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b0111000111001000 'b"
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|
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b0001110110011001011111111111011001011001011001000100010001001101011110101010 _b"
|
|
b1111110001011011010111000110100110001010000001111100111000110010100101111101 bb"
|
|
b0110000111100001110001000101000111001000000110111100110100000110000010111001 eb"
|
|
b0001011110110011010000011110010010110100101100110001000110100010101101001111 hb"
|
|
b1110010101010101000100000000001000001011110011101110100001100110001110001101 ac"
|
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b0110100111000110011111111001011001111011000111100100000010111111001111110000 yc"
|
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b01 3d"
|
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b10101110100000101101111000001100110101110111111010000000010111111000100011011010011000011010101011001111000001011011110000001111011000010001011010011001110100101010110000001101101100011001011010101101 [d"
|
|
b10100001111011110101111101001100101001011100110010110000101111000101111011011010101011011011011101110101101010101011001001000100011101011000001001011111001011000100100000001010100000110100101101101100 bd"
|
|
b01011110110101011110111011100111101110100110011101011001011110101101001001111111100111001111100111101100111100010001101101001000010110101101101110110101100001101001110010100110000111100010000110101000 id"
|
|
b00101000011010111110100001100110110001000001011011000100010101100100010110100110101010011010000001011000110110011000100001110001100101010110110010010100111000011011001000100101111111100010110100101000 pd"
|
|
b01111001100001110110100001101110001100100011110101001011011011010000100011010001100001000000100010101010100011001000110010101000100110001010110000110101001110100011001010101011000100111100111100010011 !g"
|
|
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