86 lines
2.5 KiB
Verilog
86 lines
2.5 KiB
Verilog
`include "buses.vh"
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`include "VX_define.v"
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module VX_f_d_reg (
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input wire clk,
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input wire reset,
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input wire in_valid[`NT_M1:0],
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input wire in_fwd_stall,
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input wire in_freeze,
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input wire in_clone_stall,
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output wire[31:0] out_instruction,
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output wire[31:0] out_curr_PC,
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output wire out_valid[`NT_M1:0],
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output wire[`NW_M1:0] out_warp_num,
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/* verilator lint_off UNUSED */
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input wire[31:0] in_instruction,
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input wire[31:0] in_curr_PC,
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input wire[`NW_M1:0] in_warp_num,
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input fe_inst_meta_de_t fe_inst_meta_fd
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/* verilator lint_on UNUSED */
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);
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// genvar index;
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// always @(posedge clk) begin
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// // $display("in_instruction: %x\tfe_inst_meta_fd.instruction: %x",in_instruction, fe_inst_meta_fd.instruction);
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// $error("finally");
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// assert (in_instruction == fe_inst_meta_fd.instruction);
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// assert (in_curr_PC == fe_inst_meta_fd.inst_pc);
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// assert (in_warp_num == fe_inst_meta_fd.warp_num);
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// for (index = 0; index <= `NT_M1; index = index + 1) assert (in_valid[index] == fe_inst_meta_fd.valid[index]);
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// end
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// var match;
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// always @(*) begin
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// match = ;
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// if (!match)
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// $display("in_instruction: %x, fe_inst_meta_fd.instruction: %x",in_instruction ,fe_inst_meta_fd.instruction);
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// end
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reg[31:0] instruction;
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reg[31:0] curr_PC;
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reg valid[`NT_M1:0];
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reg[`NW_M1:0] warp_num;
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integer reset_cur_thread = 0;
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always @(posedge clk or posedge reset) begin
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if(reset) begin
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instruction <= 32'h0;
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curr_PC <= 32'h0;
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warp_num <= 0;
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for (reset_cur_thread = 0; reset_cur_thread < `NT; reset_cur_thread = reset_cur_thread + 1)
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valid[reset_cur_thread] <= 1'b0;
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end else if (in_fwd_stall == 1'b1 || in_freeze == 1'b1 || in_clone_stall) begin
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// if (in_clone_stall) begin
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// $display("STALL BECAUSE OF CLONE");
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// end
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end else begin
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instruction <= in_instruction;
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valid <= in_valid;
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curr_PC <= in_curr_PC;
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warp_num <= in_warp_num;
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// instruction <= fe_inst_meta_fd.instruction;
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// valid <= fe_inst_meta_fd.valid;
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// curr_PC <= fe_inst_meta_fd.inst_pc;
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// warp_num <= fe_inst_meta_fd.warp_num;
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end
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end
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always @(*) begin
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// $display("PC in VX_f_d_reg: %h", curr_PC);
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end
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assign out_instruction = instruction;
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assign out_curr_PC = curr_PC;
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assign out_valid = valid;
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assign out_warp_num = warp_num;
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endmodule |