25 lines
483 B
Verilog
25 lines
483 B
Verilog
`include "VX_define.vh"
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module VX_onehot_encoder #(
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parameter N = 6
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) (
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input wire [N-1:0] onehot,
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output reg [`LOG2UP(N)-1:0] binary,
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output reg valid
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);
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integer i;
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always @(*) begin
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valid = 1'b0;
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binary = `LOG2UP(N)'(0);
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for (i = 0; i < N; i++) begin
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if (onehot[i]) begin
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valid = 1'b1;
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binary = `LOG2UP(N)'(i);
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end
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end
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end
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endmodule
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