238 lines
8.0 KiB
Systemverilog
238 lines
8.0 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_fpu_define.vh"
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module VX_fpu_exp import VX_fpu_pkg::*; #(
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parameter NUM_LANES = 1,
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parameter TAGW = 1
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) (
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input wire clk,
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input wire reset,
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output wire ready_in,
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input wire valid_in,
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input wire [NUM_LANES-1:0] lane_mask,
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input wire [TAGW-1:0] tag_in,
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input wire [NUM_LANES-1:0][31:0] dataa,
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output wire [NUM_LANES-1:0][31:0] result,
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output wire has_fflags,
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output wire [`FP_FLAGS_BITS-1:0] fflags,
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output wire [TAGW-1:0] tag_out,
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input wire ready_out,
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output wire valid_out
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);
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wire stall = ~ready_out && valid_out;
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wire enable = ~stall;
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fflags_t [NUM_LANES-1:0] per_lane_fflags;
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wire [NUM_LANES-1:0] lane_mask_out;
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// Convert finite FP32 to signed Q12. Values outside the useful FP32 exp
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// input range are saturated; the range-reduction logic below will turn
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// them into the appropriate overflow or underflow result.
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function automatic signed [23:0] f32_to_q12;
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input [31:0] value;
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reg [7:0] exponent;
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reg [23:0] mantissa;
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reg [63:0] magnitude;
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integer shift;
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begin
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exponent = value[30:23];
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mantissa = {1'b1, value[22:0]};
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magnitude = 0;
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if (exponent == 0) begin
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f32_to_q12 = 24'sd0;
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end else begin
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shift = integer'(exponent) - 138;
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if (shift >= 0) begin
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if (shift < 40)
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magnitude = {40'd0, mantissa} << shift;
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else
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magnitude = 64'h7fffff;
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end else if (shift > -64) begin
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magnitude = {40'd0, mantissa} >> (-shift);
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end
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if (magnitude > 64'h7fffff)
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magnitude = 64'h7fffff;
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f32_to_q12 = value[31]
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? -$signed({1'b0, magnitude[22:0]})
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: $signed({1'b0, magnitude[22:0]});
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end
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end
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endfunction
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// Q20 samples of exp(index / 16). The same LUT/interpolation structure is
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// used by the TMEM softmax engine. Range reduction guarantees index <= 11.
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function automatic [23:0] exp_frac_lut;
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input [3:0] index;
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begin
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case (index)
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4'd0: exp_frac_lut = 24'd1048576;
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4'd1: exp_frac_lut = 24'd1116203;
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4'd2: exp_frac_lut = 24'd1188192;
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4'd3: exp_frac_lut = 24'd1264824;
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4'd4: exp_frac_lut = 24'd1346398;
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4'd5: exp_frac_lut = 24'd1433233;
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4'd6: exp_frac_lut = 24'd1525669;
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4'd7: exp_frac_lut = 24'd1624066;
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4'd8: exp_frac_lut = 24'd1728810;
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4'd9: exp_frac_lut = 24'd1840308;
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4'd10: exp_frac_lut = 24'd1958998;
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4'd11: exp_frac_lut = 24'd2085342;
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default: exp_frac_lut = 24'd2219835;
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endcase
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end
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endfunction
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function automatic [23:0] interpolate_exp_frac;
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input [3:0] index;
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input [7:0] remainder;
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reg [23:0] lower;
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reg [23:0] upper;
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reg [31:0] delta;
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reg [31:0] product;
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reg [31:0] interpolated;
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begin
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lower = exp_frac_lut(index);
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upper = exp_frac_lut(index + 1'b1);
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delta = {8'd0, upper} - {8'd0, lower};
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product = delta * remainder;
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interpolated = {8'd0, lower} + ((product + 32'd128) >> 8);
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interpolate_exp_frac = interpolated[23:0];
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end
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endfunction
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// Synthesizable FP32 exponential approximation.
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//
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// x = k*ln(2) + r, 0 <= r < ln(2)
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// exp(x) = 2^k * exp(r)
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//
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// r is evaluated using the softmax-style Q12/LUT/interpolation datapath.
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// The packed return value is {NV,DZ,OF,UF,NX,result[31:0]}.
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function automatic [36:0] exp_approx_f32;
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input [31:0] value;
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reg signed [23:0] x_q12;
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integer signed k;
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integer signed rem_q12;
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integer signed exp_field;
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integer shift;
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reg [23:0] exp_r_q20;
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reg [23:0] significand;
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reg [23:0] shifted;
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reg [23:0] discarded_mask;
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reg [23:0] discarded;
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reg [23:0] halfway;
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reg [22:0] mantissa;
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reg [31:0] fp_result;
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reg [4:0] fp_flags;
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begin
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fp_result = 32'h3f800000;
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fp_flags = 5'b00000;
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if (value[30:23] == 8'hff) begin
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if (value[22:0] != 0) begin
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fp_result = 32'h7fc00000;
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fp_flags[4] = ~value[22];
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end else if (value[31]) begin
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fp_result = 32'h00000000;
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end else begin
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fp_result = 32'h7f800000;
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end
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end else if (value[30:0] != 0) begin
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x_q12 = f32_to_q12(value);
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k = integer'($signed(x_q12)) / 2839;
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rem_q12 = integer'($signed(x_q12)) - k * 2839;
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if (rem_q12 < 0) begin
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k = k - 1;
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rem_q12 = rem_q12 + 2839;
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end
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exp_r_q20 = interpolate_exp_frac(
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4'(rem_q12 >> 8), 8'(rem_q12));
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significand = {1'b1, exp_r_q20[19:0], 3'b000};
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exp_field = 127 + k;
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fp_flags[0] = 1'b1;
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if (exp_field >= 255) begin
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fp_result = 32'h7f800000;
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fp_flags[2] = 1'b1;
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end else if (exp_field > 0) begin
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mantissa = significand[22:0];
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fp_result = {1'b0, 8'(exp_field), mantissa};
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end else begin
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shift = 1 - exp_field;
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fp_flags[1] = 1'b1;
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if (shift >= 25) begin
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fp_result = 32'h00000000;
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end else begin
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shifted = significand >> shift;
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discarded_mask = (24'd1 << shift) - 1'b1;
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discarded = significand & discarded_mask;
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halfway = 24'd1 << (shift - 1);
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if ((discarded > halfway)
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|| ((discarded == halfway) && shifted[0]))
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shifted = shifted + 1'b1;
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if (shifted[23])
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fp_result = 32'h00800000;
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else
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fp_result = {9'd0, shifted[22:0]};
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end
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end
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end
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exp_approx_f32 = {fp_flags, fp_result};
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end
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endfunction
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VX_shift_register #(
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.DATAW (1 + NUM_LANES + TAGW),
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.DEPTH (`LATENCY_FEXP),
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.RESETW (1)
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) shift_reg (
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.clk (clk),
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.reset (reset),
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.enable (enable),
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.data_in ({valid_in, lane_mask, tag_in}),
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.data_out ({valid_out, lane_mask_out, tag_out})
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);
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assign ready_in = enable;
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for (genvar i = 0; i < NUM_LANES; ++i) begin
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wire [36:0] exp_approx = exp_approx_f32(dataa[i]);
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VX_shift_register #(
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.DATAW (32 + $bits(fflags_t)),
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.DEPTH (`LATENCY_FEXP)
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) shift_req_exp (
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.clk (clk),
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`UNUSED_PIN (reset),
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.enable (enable),
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.data_in ({exp_approx[31:0], exp_approx[36:32]}),
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.data_out ({result[i], per_lane_fflags[i]})
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);
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end
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assign has_fflags = 1;
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`FPU_MERGE_FFLAGS(fflags, per_lane_fflags, lane_mask_out, NUM_LANES);
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endmodule
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