28 lines
557 B
Verilog
28 lines
557 B
Verilog
`include "../VX_define.v"
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`ifndef VX_MEM_REQ_IN
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`define VX_MEM_REQ_IN
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interface VX_mem_req_inter ();
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wire[`NT_M1:0][31:0] alu_result;
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wire[2:0] mem_read;
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wire[2:0] mem_write;
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wire[4:0] rd;
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wire[1:0] wb;
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wire[4:0] rs1;
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wire[4:0] rs2;
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wire[`NT_M1:0][31:0] rd2;
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wire[31:0] PC_next;
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wire[31:0] curr_PC;
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wire[31:0] branch_offset;
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wire[2:0] branch_type;
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wire[`NT_M1:0] valid;
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wire[`NW_M1:0] warp_num;
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endinterface
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`endif |