18 lines
270 B
Verilog
18 lines
270 B
Verilog
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`include "../VX_cache/VX_cache_config.v"
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`ifndef VX_GPU_SNP_REQ
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`define VX_GPU_SNP_REQ
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interface VX_gpu_dcache_snp_req_inter ();
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// Snoop Req
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wire snp_req;
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wire [31:0] snp_req_addr;
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endinterface
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`endif |