88 lines
3.5 KiB
Verilog
88 lines
3.5 KiB
Verilog
`include "VX_define.v"
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`include "VX_cache_config.v"
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module Vortex_SOC (
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input wire clk,
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input wire reset,
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input wire[31:0] icache_response_instruction,
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output wire[31:0] icache_request_pc_address,
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// IO
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output wire io_valid,
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output wire[31:0] io_data,
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// DRAM Dcache Req
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output wire dram_req,
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output wire dram_req_write,
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output wire dram_req_read,
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output wire [31:0] dram_req_addr,
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output wire [31:0] dram_req_size,
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output wire [31:0] dram_req_data[`DBANK_LINE_SIZE_RNG],
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output wire [31:0] dram_expected_lat,
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// DRAM Dcache Res
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output wire dram_fill_accept,
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input wire dram_fill_rsp,
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input wire [31:0] dram_fill_rsp_addr,
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input wire [31:0] dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG],
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// DRAM Icache Req
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output wire I_dram_req,
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output wire I_dram_req_write,
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output wire I_dram_req_read,
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output wire [31:0] I_dram_req_addr,
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output wire [31:0] I_dram_req_size,
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output wire [31:0] I_dram_req_data[`DBANK_LINE_SIZE_RNG],
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output wire [31:0] I_dram_expected_lat,
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// DRAM Icache Res
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output wire I_dram_fill_accept,
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input wire I_dram_fill_rsp,
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input wire [31:0] I_dram_fill_rsp_addr,
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input wire [31:0] I_dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG],
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output wire out_ebreak
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);
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Vortex vortex_core(
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.clk (clk),
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.reset (reset),
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.icache_response_instruction(icache_response_instruction),
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.icache_request_pc_address (icache_request_pc_address),
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.io_valid (io_valid),
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.io_data (io_data),
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.dram_req (dram_req),
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.dram_req_write (dram_req_write),
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.dram_req_read (dram_req_read),
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.dram_req_addr (dram_req_addr),
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.dram_req_size (dram_req_size),
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.dram_req_data (dram_req_data),
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.dram_expected_lat (dram_expected_lat),
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.dram_fill_accept (dram_fill_accept),
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.dram_fill_rsp (dram_fill_rsp),
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.dram_fill_rsp_addr (dram_fill_rsp_addr),
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.dram_fill_rsp_data (dram_fill_rsp_data),
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.I_dram_req (I_dram_req),
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.I_dram_req_write (I_dram_req_write),
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.I_dram_req_read (I_dram_req_read),
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.I_dram_req_addr (I_dram_req_addr),
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.I_dram_req_size (I_dram_req_size),
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.I_dram_req_data (I_dram_req_data),
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.I_dram_expected_lat (I_dram_expected_lat),
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.I_dram_fill_accept (I_dram_fill_accept),
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.I_dram_fill_rsp (I_dram_fill_rsp),
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.I_dram_fill_rsp_addr (I_dram_fill_rsp_addr),
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.I_dram_fill_rsp_data (I_dram_fill_rsp_data),
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.out_ebreak (out_ebreak)
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);
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endmodule |