302 lines
12 KiB
Systemverilog
302 lines
12 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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module VX_operands import VX_gpu_pkg::*; #(
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parameter CORE_ID = 0,
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parameter CACHE_ENABLE = 0
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) (
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input wire clk,
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input wire reset,
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VX_writeback_if.slave writeback_if [`ISSUE_WIDTH],
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VX_ibuffer_if.slave scoreboard_if [`ISSUE_WIDTH],
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VX_operands_if.master operands_if [`ISSUE_WIDTH]
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);
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`UNUSED_PARAM (CORE_ID)
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localparam DATAW = `UUID_WIDTH + ISSUE_WIS_W + `NUM_THREADS + `XLEN + 1 + `EX_BITS + `INST_OP_BITS + `INST_MOD_BITS + 1 + 1 + `XLEN + `NR_BITS;
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localparam STATE_IDLE = 2'd0;
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localparam STATE_FETCH1 = 2'd1;
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localparam STATE_FETCH2 = 2'd2;
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localparam STATE_FETCH3 = 2'd3;
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localparam STATE_BITS = 2;
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for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
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wire [`NUM_THREADS-1:0][`XLEN-1:0] gpr_rd_data;
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reg [`NR_BITS-1:0] gpr_rd_rid, gpr_rd_rid_n;
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reg [ISSUE_WIS_W-1:0] gpr_rd_wis, gpr_rd_wis_n;
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reg [`NUM_THREADS-1:0][`XLEN-1:0] cache_data [ISSUE_RATIO-1:0];
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reg [`NUM_THREADS-1:0][`XLEN-1:0] cache_data_n [ISSUE_RATIO-1:0];
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reg [`NR_BITS-1:0] cache_reg [ISSUE_RATIO-1:0];
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reg [`NR_BITS-1:0] cache_reg_n [ISSUE_RATIO-1:0];
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reg [`NUM_THREADS-1:0] cache_tmask [ISSUE_RATIO-1:0];
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reg [`NUM_THREADS-1:0] cache_tmask_n [ISSUE_RATIO-1:0];
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reg [ISSUE_RATIO-1:0] cache_eop, cache_eop_n;
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reg [`NUM_THREADS-1:0][`XLEN-1:0] rs1_data, rs1_data_n;
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reg [`NUM_THREADS-1:0][`XLEN-1:0] rs2_data, rs2_data_n;
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reg [`NUM_THREADS-1:0][`XLEN-1:0] rs3_data, rs3_data_n;
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reg [STATE_BITS-1:0] state, state_n;
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reg [`NR_BITS-1:0] rs2, rs2_n;
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reg [`NR_BITS-1:0] rs3, rs3_n;
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reg rs2_ready, rs2_ready_n;
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reg rs3_ready, rs3_ready_n;
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reg data_ready, data_ready_n;
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wire is_rs1_zero = (scoreboard_if[i].data.rs1 == 0);
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wire is_rs2_zero = (scoreboard_if[i].data.rs2 == 0);
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wire is_rs3_zero = (scoreboard_if[i].data.rs3 == 0);
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VX_operands_if staging_if();
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always @(*) begin
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state_n = state;
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rs2_n = rs2;
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rs3_n = rs3;
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rs2_ready_n = rs2_ready;
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rs3_ready_n = rs3_ready;
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rs1_data_n = rs1_data;
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rs2_data_n = rs2_data;
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rs3_data_n = rs3_data;
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cache_data_n = cache_data;
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cache_reg_n = cache_reg;
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cache_tmask_n= cache_tmask;
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cache_eop_n = cache_eop;
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gpr_rd_rid_n = gpr_rd_rid;
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gpr_rd_wis_n = gpr_rd_wis;
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data_ready_n = data_ready;
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case (state)
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STATE_IDLE: begin
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if (staging_if.valid && staging_if.ready) begin
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data_ready_n = 0;
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end
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if (scoreboard_if[i].valid && data_ready_n == 0) begin
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data_ready_n = 1;
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if (is_rs3_zero || (CACHE_ENABLE != 0 &&
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scoreboard_if[i].data.rs3 == cache_reg[scoreboard_if[i].data.wis] &&
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(scoreboard_if[i].data.tmask & cache_tmask[scoreboard_if[i].data.wis]) == scoreboard_if[i].data.tmask)) begin
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rs3_data_n = (is_rs3_zero || CACHE_ENABLE == 0) ? '0 : cache_data[scoreboard_if[i].data.wis];
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rs3_ready_n = 1;
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end else begin
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rs3_ready_n = 0;
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gpr_rd_rid_n = scoreboard_if[i].data.rs3;
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data_ready_n = 0;
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state_n = STATE_FETCH3;
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end
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if (is_rs2_zero || (CACHE_ENABLE != 0 &&
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scoreboard_if[i].data.rs2 == cache_reg[scoreboard_if[i].data.wis] &&
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(scoreboard_if[i].data.tmask & cache_tmask[scoreboard_if[i].data.wis]) == scoreboard_if[i].data.tmask)) begin
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rs2_data_n = (is_rs2_zero || CACHE_ENABLE == 0) ? '0 : cache_data[scoreboard_if[i].data.wis];
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rs2_ready_n = 1;
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end else begin
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rs2_ready_n = 0;
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gpr_rd_rid_n = scoreboard_if[i].data.rs2;
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data_ready_n = 0;
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state_n = STATE_FETCH2;
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end
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if (is_rs1_zero || (CACHE_ENABLE != 0 &&
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scoreboard_if[i].data.rs1 == cache_reg[scoreboard_if[i].data.wis] &&
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(scoreboard_if[i].data.tmask & cache_tmask[scoreboard_if[i].data.wis]) == scoreboard_if[i].data.tmask)) begin
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rs1_data_n = (is_rs1_zero || CACHE_ENABLE == 0) ? '0 : cache_data[scoreboard_if[i].data.wis];
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end else begin
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gpr_rd_rid_n = scoreboard_if[i].data.rs1;
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data_ready_n = 0;
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state_n = STATE_FETCH1;
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end
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end
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gpr_rd_wis_n = scoreboard_if[i].data.wis;
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rs2_n = scoreboard_if[i].data.rs2;
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rs3_n = scoreboard_if[i].data.rs3;
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end
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STATE_FETCH1: begin
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rs1_data_n = gpr_rd_data;
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if (~rs2_ready) begin
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gpr_rd_rid_n = rs2;
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state_n = STATE_FETCH2;
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end else if (~rs3_ready) begin
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gpr_rd_rid_n = rs3;
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state_n = STATE_FETCH3;
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end else begin
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data_ready_n = 1;
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state_n = STATE_IDLE;
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end
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end
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STATE_FETCH2: begin
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rs2_data_n = gpr_rd_data;
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if (~rs3_ready) begin
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gpr_rd_rid_n = rs3;
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state_n = STATE_FETCH3;
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end else begin
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data_ready_n = 1;
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state_n = STATE_IDLE;
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end
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end
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STATE_FETCH3: begin
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rs3_data_n = gpr_rd_data;
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data_ready_n = 1;
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state_n = STATE_IDLE;
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end
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endcase
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if (CACHE_ENABLE != 0 && writeback_if[i].valid) begin
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if ((cache_reg[writeback_if[i].data.wis] == writeback_if[i].data.rd)
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|| (cache_eop[writeback_if[i].data.wis] && writeback_if[i].data.sop)) begin
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for (integer j = 0; j < `NUM_THREADS; ++j) begin
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if (writeback_if[i].data.tmask[j]) begin
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cache_data_n[writeback_if[i].data.wis][j] = writeback_if[i].data.data[j];
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end
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end
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cache_reg_n[writeback_if[i].data.wis] = writeback_if[i].data.rd;
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cache_eop_n[writeback_if[i].data.wis] = writeback_if[i].data.eop;
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cache_tmask_n[writeback_if[i].data.wis] = writeback_if[i].data.sop ? writeback_if[i].data.tmask :
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(cache_tmask_n[writeback_if[i].data.wis] | writeback_if[i].data.tmask);
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end
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end
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end
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always @(posedge clk) begin
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if (reset) begin
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state <= STATE_IDLE;
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gpr_rd_rid <= '0;
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gpr_rd_wis <= '0;
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cache_eop <= {ISSUE_RATIO{1'b1}};
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data_ready <= 0;
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end else begin
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state <= state_n;
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rs2 <= rs2_n;
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rs3 <= rs3_n;
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rs2_ready <= rs2_ready_n;
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rs3_ready <= rs3_ready_n;
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rs1_data <= rs1_data_n;
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rs2_data <= rs2_data_n;
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rs3_data <= rs3_data_n;
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gpr_rd_rid <= gpr_rd_rid_n;
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gpr_rd_wis <= gpr_rd_wis_n;
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cache_data <= cache_data_n;
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cache_reg <= cache_reg_n;
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cache_tmask <= cache_tmask_n;
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cache_eop <= cache_eop_n;
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data_ready <= data_ready_n;
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end
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end
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// GPR banks
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`ifdef GPR_RESET
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reg wr_enabled = 0;
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always @(posedge clk) begin
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if (reset) begin
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wr_enabled <= 1;
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end
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end
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`else
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wire wr_enabled = 1;
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`endif
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for (genvar j = 0; j < `NUM_THREADS; ++j) begin
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VX_dp_ram #(
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.DATAW (`XLEN),
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.SIZE (`NUM_REGS * ISSUE_RATIO),
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`ifdef GPR_RESET
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.INIT_ENABLE (1),
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.INIT_VALUE (0),
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`endif
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.NO_RWCHECK (1)
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) gpr_ram (
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.clk (clk),
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.read (1'b1),
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`UNUSED_PIN (wren),
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.write (wr_enabled && writeback_if[i].valid && writeback_if[i].data.tmask[j]),
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.waddr (wis_to_addr(writeback_if[i].data.rd, writeback_if[i].data.wis)),
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.wdata (writeback_if[i].data.data[j]),
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.raddr (wis_to_addr(gpr_rd_rid, gpr_rd_wis)),
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.rdata (gpr_rd_data[j])
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);
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end
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// staging buffer
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`RESET_RELAY (stg_buf_reset, reset);
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VX_elastic_buffer #(
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.DATAW (DATAW)
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) stg_buf (
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.clk (clk),
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.reset (stg_buf_reset),
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.valid_in (scoreboard_if[i].valid),
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.ready_in (scoreboard_if[i].ready),
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.data_in ({
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scoreboard_if[i].data.uuid,
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scoreboard_if[i].data.wis,
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scoreboard_if[i].data.tmask,
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scoreboard_if[i].data.PC,
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scoreboard_if[i].data.wb,
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scoreboard_if[i].data.ex_type,
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scoreboard_if[i].data.op_type,
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scoreboard_if[i].data.op_mod,
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scoreboard_if[i].data.use_PC,
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scoreboard_if[i].data.use_imm,
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scoreboard_if[i].data.imm,
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scoreboard_if[i].data.rd}),
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.data_out ({
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staging_if.data.uuid,
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staging_if.data.wis,
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staging_if.data.tmask,
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staging_if.data.PC,
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staging_if.data.wb,
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staging_if.data.ex_type,
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staging_if.data.op_type,
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staging_if.data.op_mod,
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staging_if.data.use_PC,
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staging_if.data.use_imm,
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staging_if.data.imm,
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staging_if.data.rd}),
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.valid_out (staging_if.valid),
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.ready_out (staging_if.ready)
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);
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assign staging_if.data.rs1_data = rs1_data;
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assign staging_if.data.rs2_data = rs2_data;
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assign staging_if.data.rs3_data = rs3_data;
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// output buffer
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wire valid_stg, ready_stg;
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assign valid_stg = staging_if.valid && data_ready;
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assign staging_if.ready = ready_stg && data_ready;
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`RESET_RELAY (out_buf_reset, reset);
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VX_elastic_buffer #(
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.DATAW (DATAW + (3 * `NUM_THREADS * `XLEN)),
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.SIZE (2),
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.OUT_REG (2)
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) out_buf (
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.clk (clk),
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.reset (out_buf_reset),
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.valid_in (valid_stg),
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.ready_in (ready_stg),
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.data_in (staging_if.data),
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.data_out (operands_if[i].data),
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.valid_out (operands_if[i].valid),
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.ready_out (operands_if[i].ready)
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);
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end
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endmodule
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