17 lines
277 B
Verilog
17 lines
277 B
Verilog
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module VX_one_counter (
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input wire[`NW-1:0] valids,
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output reg[`NW_M1:0] ones_found
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);
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integer i;
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always @(*) begin
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ones_found = 0;
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for (i = `NW-1; i >= 0; i = i - 1) begin
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if (valids[i]) begin
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ones_found = ones_found + 1;
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end
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end
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end
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endmodule |