26 lines
478 B
Verilog
26 lines
478 B
Verilog
`include "VX_platform.vh"
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`TRACING_OFF
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module VX_reset_relay #(
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parameter ASYNC = 0
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) (
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input wire clk,
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input wire reset,
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output wire reset_o
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);
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(* preserve *) reg reset_r;
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if (ASYNC) begin
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always @(posedge clk or posedge reset) begin
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reset_r <= reset;
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end
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end else begin
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always @(posedge clk) begin
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reset_r <= reset;
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end
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end
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assign reset_o = reset_r;
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endmodule
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`TRACING_ON |