41 lines
956 B
Verilog
41 lines
956 B
Verilog
`ifndef VX_DECODE_IF
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`define VX_DECODE_IF
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`include "VX_define.vh"
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interface VX_decode_if ();
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wire [`NUM_THREADS-1:0] valid;
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wire [`NW_BITS-1:0] warp_num;
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wire [31:0] curr_PC;
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wire [31:0] next_PC;
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wire [`EX_BITS-1:0] ex_type;
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wire [`OP_BITS-1:0] instr_op;
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wire [`NR_BITS-1:0] rd;
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wire [`NR_BITS-1:0] rs1;
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wire [`NR_BITS-1:0] rs2;
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wire [31:0] imm;
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wire rs1_is_PC;
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wire rs2_is_imm;
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wire use_rs1;
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wire use_rs2;
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// FP states
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wire [`NR_BITS-1:0] rs3;
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wire use_rs3;
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wire rd_is_fp;
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wire rs1_is_fp;
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wire rs2_is_fp;
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wire [`FRM_BITS-1:0] frm;
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wire wb;
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wire ready;
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endinterface
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`endif |