29 lines
775 B
Verilog
29 lines
775 B
Verilog
`ifndef VX_INSTR_SCHED_IF
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`define VX_INSTR_SCHED_IF
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`include "VX_define.vh"
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interface VX_instr_sched_if ();
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wire valid;
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wire [`NW_BITS-1:0] wid;
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wire [`NW_BITS-1:0] wid_n;
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wire [`NUM_THREADS-1:0] tmask;
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wire [31:0] PC;
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wire [`EX_BITS-1:0] ex_type;
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wire [`OP_BITS-1:0] op_type;
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wire [`MOD_BITS-1:0] op_mod;
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wire wb;
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wire [`NR_BITS-1:0] rd;
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wire [`NR_BITS-1:0] rs1;
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wire [`NR_BITS-1:0] rs2;
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wire [`NR_BITS-1:0] rs3;
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wire [31:0] imm;
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wire use_PC;
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wire use_imm;
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wire [`NUM_REGS-1:0] used_regs;
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wire ready;
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endinterface
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`endif |