203 lines
6.7 KiB
Verilog
203 lines
6.7 KiB
Verilog
`include "VX_define.vh"
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module VX_mul_unit #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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// Inputs
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VX_mul_req_if mul_req_if,
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// Outputs
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VX_exu_to_cmt_if mul_commit_if
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);
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localparam MULQ_BITS = `LOG2UP(`MULQ_SIZE);
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wire [`MUL_BITS-1:0] alu_op = mul_req_if.op;
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wire [`NUM_THREADS-1:0][31:0] alu_in1 = mul_req_if.rs1_data;
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wire [`NUM_THREADS-1:0][31:0] alu_in2 = mul_req_if.rs2_data;
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wire [`NW_BITS-1:0] rsp_wid;
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wire [`NUM_THREADS-1:0] rsp_thread_mask;
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wire [31:0] rsp_curr_PC;
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wire [`NR_BITS-1:0] rsp_rd;
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wire rsp_wb;
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wire [MULQ_BITS-1:0] tag_in, tag_out;
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wire valid_out;
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wire stall_out;
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wire mulq_full;
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wire mulq_push = mul_req_if.valid && mul_req_if.ready;
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wire mulq_pop = valid_out && ~stall_out;
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VX_cam_buffer #(
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.DATAW (`NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1),
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.SIZE (`MULQ_SIZE)
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) mul_queue (
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.clk (clk),
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.reset (reset),
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.acquire_slot (mulq_push),
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.write_addr (tag_in),
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.read_addr (tag_out),
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.release_addr (tag_out),
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.write_data ({mul_req_if.wid, mul_req_if.thread_mask, mul_req_if.curr_PC, mul_req_if.rd, mul_req_if.wb}),
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.read_data ({rsp_wid, rsp_thread_mask, rsp_curr_PC, rsp_rd, rsp_wb}),
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.release_slot (mulq_pop),
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.full (mulq_full)
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);
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///////////////////////////////////////////////////////////////////////////
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wire [`NUM_THREADS-1:0][31:0] mul_result;
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wire is_mulw = (alu_op == `MUL_MUL);
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wire is_mulw_out;
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wire stall_mul;
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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wire [32:0] mul_in1 = {(alu_op != `MUL_MULHU) & alu_in1[i][31], alu_in1[i]};
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wire [32:0] mul_in2 = {(alu_op != `MUL_MULHU && alu_op != `MUL_MULHSU) & alu_in2[i][31], alu_in2[i]};
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wire [63:0] mul_result_tmp;
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VX_multiplier #(
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.WIDTHA(33),
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.WIDTHB(33),
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.WIDTHP(64),
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.SIGNED(1),
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.PIPELINE(`LATENCY_IMUL)
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) multiplier (
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.clk(clk),
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.reset(reset),
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.clk_en(~stall_mul),
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.dataa(mul_in1),
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.datab(mul_in2),
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.result(mul_result_tmp)
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);
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assign mul_result[i] = is_mulw_out ? mul_result_tmp[31:0] : mul_result_tmp[63:32];
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end
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wire [MULQ_BITS-1:0] mul_tag;
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wire mul_valid_out;
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wire mul_fire = mul_req_if.valid && mul_req_if.ready && ~`IS_DIV_OP(alu_op);
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VX_shift_register #(
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.DATAW(1 + MULQ_BITS + 1),
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.DEPTH(`LATENCY_IMUL)
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) mul_shift_reg (
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.clk(clk),
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.reset(reset),
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.enable(~stall_mul),
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.in({mul_fire, tag_in, is_mulw}),
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.out({mul_valid_out, mul_tag, is_mulw_out})
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);
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///////////////////////////////////////////////////////////////////////////
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wire [`NUM_THREADS-1:0][31:0] div_result;
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wire is_div = (alu_op == `MUL_DIV || alu_op == `MUL_DIVU);
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wire is_signed_div = (alu_op == `MUL_DIV || alu_op == `MUL_REM);
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reg [`NUM_THREADS-1:0] is_div_qual;
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wire is_div_out;
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wire stall_div;
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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reg [31:0] div_in1_qual, div_in2_qual;
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reg [32:0] div_in1, div_in2;
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wire [31:0] div_result_tmp, rem_result_tmp;
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// handle divide by zero
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always @(*) begin
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if (~stall_div) begin
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is_div_qual[i] = is_div;
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div_in1_qual = alu_in1[i];
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div_in2_qual = alu_in2[i];
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if (0 == alu_in2[i]) begin
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div_in2_qual = 1;
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if (is_div) begin
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div_in1_qual = 32'hFFFFFFFF; // quotient = (0xFFFFFFFF / 1)
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end else begin
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is_div_qual[i] = 1; // remainder = (in1 / 1)
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end
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end
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end
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end
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// latch divider inputs
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always @(posedge clk) begin
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if (~stall_div) begin
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div_in1 <= {is_signed_div & alu_in1[i][31], div_in1_qual};
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div_in2 <= {is_signed_div & alu_in2[i][31], div_in2_qual};
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end
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end
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VX_divide #(
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.WIDTHN(33),
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.WIDTHD(33),
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.WIDTHQ(32),
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.WIDTHR(32),
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.NSIGNED(1),
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.DSIGNED(1),
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.PIPELINE(`LATENCY_IDIV)
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) divide (
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.clk(clk),
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.reset(reset),
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.clk_en(~stall_div),
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.numer(div_in1),
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.denom(div_in2),
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.quotient(div_result_tmp),
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.remainder(rem_result_tmp)
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);
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assign div_result[i] = is_div_out ? div_result_tmp : rem_result_tmp;
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end
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wire [MULQ_BITS-1:0] div_tag;
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wire div_valid_out;
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wire div_fire = mul_req_if.valid && mul_req_if.ready && `IS_DIV_OP(alu_op);
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VX_shift_register #(
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.DATAW(1 + MULQ_BITS + 1),
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.DEPTH(`LATENCY_IDIV + 1)
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) div_shift_reg (
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.clk(clk),
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.reset(reset),
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.enable(~stall_div),
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.in({div_fire, tag_in, (| is_div_qual)}),
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.out({div_valid_out, div_tag, is_div_out})
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);
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///////////////////////////////////////////////////////////////////////////
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wire arbiter_hazard = mul_valid_out && div_valid_out;
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assign stall_out = ~mul_commit_if.ready && mul_commit_if.valid;
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assign stall_mul = stall_out || mulq_full;
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assign stall_div = stall_out || mulq_full
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|| arbiter_hazard; // arbitration prioritizes MUL
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wire stall_in = stall_mul || stall_div;
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assign valid_out = mul_valid_out || div_valid_out;
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assign tag_out = mul_valid_out ? mul_tag : div_tag;
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wire [`NUM_THREADS-1:0][31:0] result = mul_valid_out ? mul_result : div_result;
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VX_generic_register #(
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.N(1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32))
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) alu_reg (
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.clk (clk),
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.reset (reset),
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.stall (stall_out),
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.flush (0),
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.in ({valid_out, rsp_wid, rsp_thread_mask, rsp_curr_PC, rsp_rd, rsp_wb, result}),
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.out ({mul_commit_if.valid, mul_commit_if.wid, mul_commit_if.thread_mask, mul_commit_if.curr_PC, mul_commit_if.rd, mul_commit_if.wb, mul_commit_if.data})
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);
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// can accept new request?
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assign mul_req_if.ready = ~stall_in;
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endmodule |