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vortex
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1a29007bc7d3287c06b5f482ea07cba9dca21d3e
vortex
/
models
/
memory
/
cln28hpc
/
rf2_32x128_wm1
/
vsim
History
Lingjun Zhu
50d567d70c
Removed unnessary Verilog files, linked memory tech files, having problem with memory instatiation
2019-10-28 14:49:55 -04:00
..
work
Removed unnessary Verilog files, linked memory tech files, having problem with memory instatiation
2019-10-28 14:49:55 -04:00
rf2_32x128_wm1_tb.v
Created a testbench and simulated the read/write of the register file
2019-10-18 22:55:34 -04:00
rf_tb.cr.mti
Removed unnessary Verilog files, linked memory tech files, having problem with memory instatiation
2019-10-28 14:49:55 -04:00
rf_tb.mpf
Removed unnessary Verilog files, linked memory tech files, having problem with memory instatiation
2019-10-28 14:49:55 -04:00
transcript
Removed unnessary Verilog files, linked memory tech files, having problem with memory instatiation
2019-10-28 14:49:55 -04:00
vsim.wlf
Removed unnessary Verilog files, linked memory tech files, having problem with memory instatiation
2019-10-28 14:49:55 -04:00
