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18c1dc2f0e8c941903f549ce997df99f9477a8d7
vortex/hw/rtl/cache
History
Blaise Tine 18c1dc2f0e fixed interface modports
2021-09-28 02:42:04 -07:00
..
VX_bank.v
code refactoring for Vivado, sv2v, and yosys compatibility
2021-09-27 08:55:10 -04:00
VX_cache_define.vh
code refactoring for Vivado, sv2v, and yosys compatibility
2021-09-27 08:55:10 -04:00
VX_cache.v
code refactoring for Vivado, sv2v, and yosys compatibility
2021-09-27 08:55:10 -04:00
VX_core_req_bank_sel.v
code refactoring for Vivado, sv2v, and yosys compatibility
2021-09-27 08:55:10 -04:00
VX_core_rsp_merge.v
Updated README and synthesis scripts
2021-09-22 07:50:47 -07:00
VX_data_access.v
code refactoring for Vivado, sv2v, and yosys compatibility
2021-09-27 08:55:10 -04:00
VX_flush_ctrl.v
refactoring cache_config
2021-05-27 14:41:46 -07:00
VX_miss_resrv.v
code refactoring for Vivado, sv2v, and yosys compatibility
2021-09-27 08:55:10 -04:00
VX_nc_bypass.v
code refactoring for Vivado, sv2v, and yosys compatibility
2021-09-27 08:55:10 -04:00
VX_shared_mem.v
fixed interface modports
2021-09-28 02:42:04 -07:00
VX_tag_access.v
cache bank pipeline optimization
2021-09-14 02:09:35 -07:00
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