Blaise Tine 1795980a52 L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization

2020-11-21 09:47:56 -08:00

..

VX_bank_core_req_arb.v

reset networks optimization

2020-11-16 01:12:02 -08:00

VX_bank.v

L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization

2020-11-21 09:47:56 -08:00

VX_cache_config.vh

L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization

2020-11-21 09:47:56 -08:00

VX_cache_core_req_bank_sel.v

L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization

2020-11-21 09:47:56 -08:00

VX_cache_core_rsp_merge.v

fixed shared memory addressing critical path, fixed VX_fp_noncomp output bug

2020-11-17 00:27:24 -08:00

VX_cache_dram_req_arb.v

refactoring all arbiters with buffering for request count > 2, optimized the cache core response module in critical path when running as L2

2020-11-08 01:31:46 -08:00

VX_cache_miss_resrv.v

L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization

2020-11-21 09:47:56 -08:00

VX_cache.v

L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization

2020-11-21 09:47:56 -08:00

VX_data_access.v

fixed shared memory addressing critical path, fixed VX_fp_noncomp output bug

2020-11-17 00:27:24 -08:00

VX_data_store.v

cache refactoring - phase 3 - added dedicated pipeline stage for tag access

2020-11-04 03:21:30 -08:00

VX_snp_forwarder.v

L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization

2020-11-21 09:47:56 -08:00

VX_snp_rsp_arb.v

L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization

2020-11-21 09:47:56 -08:00

VX_tag_access.v

minor fix

2020-11-16 08:23:16 -08:00

VX_tag_store.v

fixed redundnat cache fill with dirty block, fixed cache tag_store critical path

2020-11-10 08:32:34 -08:00