61 lines
2.1 KiB
Verilog
61 lines
2.1 KiB
Verilog
`include "VX_platform.vh"
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`TRACING_OFF
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module VX_find_first #(
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parameter N = 1,
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parameter DATAW = 1,
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parameter REVERSE = 0,
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localparam LOGN = $clog2(N)
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) (
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input wire [N-1:0][DATAW-1:0] data_i,
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input wire [N-1:0] valid_i,
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output wire [DATAW-1:0] data_o,
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output wire valid_o
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);
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if (N > 1) begin
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wire [N-1:0] valid_r;
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wire [N-1:0][DATAW-1:0] data_r;
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for (genvar i = 0; i < N; ++i) begin
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assign valid_r[i] = REVERSE ? valid_i[N-1-i] : valid_i[i];
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assign data_r[i] = REVERSE ? data_i[N-1-i] : data_i[i];
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end
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`IGNORE_WARNINGS_BEGIN
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wire [2**LOGN-1:0] s_n;
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wire [2**LOGN-1:0][DATAW-1:0] d_n;
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`IGNORE_WARNINGS_END
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for (genvar i = 0; i < LOGN; ++i) begin
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if (i == (LOGN-1)) begin
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for (genvar j = 0; j < 2**i; ++j) begin
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if ((j*2) < (N-1)) begin
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assign s_n[2**i-1+j] = valid_r[j*2] | valid_r[j*2+1];
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assign d_n[2**i-1+j] = valid_r[j*2] ? data_r[j*2] : data_r[j*2+1];
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end
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if ((j*2) == (N-1)) begin
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assign s_n[2**i-1+j] = valid_r[j*2];
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assign d_n[2**i-1+j] = data_r[j*2];
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end
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if ((j*2) > (N-1)) begin
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assign s_n[2**i-1+j] = 0;
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assign d_n[2**i-1+j] = 'x;
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end
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end
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end else begin
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for (genvar j = 0; j < 2**i; ++j) begin
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assign s_n[2**i-1+j] = s_n[2**(i+1)-1+j*2] | s_n[2**(i+1)-1+j*2+1];
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assign d_n[2**i-1+j] = s_n[2**(i+1)-1+j*2] ? d_n[2**(i+1)-1+j*2] : d_n[2**(i+1)-1+j*2+1];
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end
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end
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end
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assign valid_o = s_n[0];
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assign data_o = d_n[0];
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end else begin
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assign valid_o = valid_i;
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assign data_o = data_i[0];
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end
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endmodule
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`TRACING_ON |