578 lines
24 KiB
Verilog
578 lines
24 KiB
Verilog
`include "VX_cache_config.vh"
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module VX_cache #(
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parameter CACHE_ID = 0,
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// Size of cache in bytes
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parameter CACHE_SIZE = 8092,
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// Size of line inside a bank in bytes
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parameter BANK_LINE_SIZE = 16,
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// Number of banks
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parameter NUM_BANKS = 4,
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// Size of a word in bytes
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parameter WORD_SIZE = 4,
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// Number of Word requests per cycle
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parameter NUM_REQS = NUM_BANKS,
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// Core Request Queue Size
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parameter CREQ_SIZE = 4,
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// Miss Reserv Queue Knob
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parameter MSHR_SIZE = 8,
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// DRAM Response Queue Size
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parameter DRFQ_SIZE = 4,
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// Snoop Req Queue Size
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parameter SNRQ_SIZE = 4,
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// Core Writeback Queue Size
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parameter CWBQ_SIZE = 4,
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// DRAM Request Queue Size
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parameter DREQ_SIZE = 4,
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// Snoop Response Size
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parameter SNPQ_SIZE = 4,
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// Enable cache writeable
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parameter WRITE_ENABLE = 1,
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// Enable dram update
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parameter DRAM_ENABLE = 1,
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// Enable cache flush
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parameter FLUSH_ENABLE = 1,
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// size of tag id in core request tag
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parameter CORE_TAG_ID_BITS = $clog2(MSHR_SIZE),
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// core request tag size
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parameter CORE_TAG_WIDTH = CORE_TAG_ID_BITS,
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// dram request tag size
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parameter DRAM_TAG_WIDTH = (32 - $clog2(BANK_LINE_SIZE)),
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// Snooping request tag width
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parameter SNP_TAG_WIDTH = 1
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) (
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`SCOPE_IO_VX_cache
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input wire clk,
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input wire reset,
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// Core request
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input wire [NUM_REQS-1:0] core_req_valid,
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input wire [`CORE_REQ_TAG_COUNT-1:0] core_req_rw,
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input wire [NUM_REQS-1:0][WORD_SIZE-1:0] core_req_byteen,
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input wire [NUM_REQS-1:0][`WORD_ADDR_WIDTH-1:0] core_req_addr,
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input wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_req_data,
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input wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_req_tag,
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output wire core_req_ready,
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// Core response
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output wire [NUM_REQS-1:0] core_rsp_valid,
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output wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_rsp_data,
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output wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag,
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input wire core_rsp_ready,
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// PERF
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`ifdef PERF_ENABLE
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VX_perf_cache_if perf_cache_if,
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`endif
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// DRAM request
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output wire dram_req_valid,
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output wire dram_req_rw,
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output wire [BANK_LINE_SIZE-1:0] dram_req_byteen,
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output wire [`DRAM_ADDR_WIDTH-1:0] dram_req_addr,
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output wire [`BANK_LINE_WIDTH-1:0] dram_req_data,
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output wire [DRAM_TAG_WIDTH-1:0] dram_req_tag,
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input wire dram_req_ready,
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// DRAM response
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input wire dram_rsp_valid,
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input wire [`BANK_LINE_WIDTH-1:0] dram_rsp_data,
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input wire [DRAM_TAG_WIDTH-1:0] dram_rsp_tag,
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output wire dram_rsp_ready,
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// Snoop request
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input wire snp_req_valid,
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input wire [`DRAM_ADDR_WIDTH-1:0] snp_req_addr,
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input wire snp_req_inv,
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input wire [SNP_TAG_WIDTH-1:0] snp_req_tag,
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output wire snp_req_ready,
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// Snoop response
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output wire snp_rsp_valid,
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output wire [SNP_TAG_WIDTH-1:0] snp_rsp_tag,
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input wire snp_rsp_ready,
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output wire [NUM_BANKS-1:0] miss_vec
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);
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`STATIC_ASSERT(NUM_BANKS <= NUM_REQS, ("invalid value"))
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wire [NUM_BANKS-1:0][NUM_REQS-1:0] per_bank_valid;
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wire [NUM_BANKS-1:0] per_bank_core_req_ready;
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wire [NUM_BANKS-1:0] per_bank_core_rsp_valid;
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wire [NUM_BANKS-1:0][`REQS_BITS-1:0] per_bank_core_rsp_tid;
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wire [NUM_BANKS-1:0][`WORD_WIDTH-1:0] per_bank_core_rsp_data;
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wire [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_rsp_tag;
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wire [NUM_BANKS-1:0] per_bank_core_rsp_ready;
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wire [NUM_BANKS-1:0] per_bank_dram_req_valid;
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wire [NUM_BANKS-1:0] per_bank_dram_req_rw;
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wire [NUM_BANKS-1:0][BANK_LINE_SIZE-1:0] per_bank_dram_req_byteen;
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wire [NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] per_bank_dram_req_addr;
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wire [NUM_BANKS-1:0][`BANK_LINE_WIDTH-1:0] per_bank_dram_req_data;
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wire [NUM_BANKS-1:0] per_bank_dram_req_ready;
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wire [NUM_BANKS-1:0] per_bank_dram_rsp_ready;
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wire [NUM_BANKS-1:0] per_bank_snp_req_ready;
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wire [NUM_BANKS-1:0] per_bank_snp_rsp_valid;
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wire [NUM_BANKS-1:0][SNP_TAG_WIDTH-1:0] per_bank_snp_rsp_tag;
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wire [NUM_BANKS-1:0] per_bank_snp_rsp_ready;
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wire [NUM_BANKS-1:0] per_bank_miss;
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assign miss_vec = per_bank_miss;
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`ifdef PERF_ENABLE
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wire [NUM_BANKS-1:0] perf_msrq_stall_per_bank;
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wire [NUM_BANKS-1:0] perf_total_stall_per_bank;
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wire [NUM_BANKS-1:0] perf_evict_per_bank;
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wire [NUM_BANKS-1:0] perf_read_miss_per_bank;
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wire [NUM_BANKS-1:0] perf_write_miss_per_bank;
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`endif
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if (NUM_BANKS == 1) begin
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assign snp_req_ready = per_bank_snp_req_ready;
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end else begin
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assign snp_req_ready = per_bank_snp_req_ready[`DRAM_ADDR_BANK(snp_req_addr)];
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end
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VX_cache_core_req_bank_sel #(
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.BANK_LINE_SIZE (BANK_LINE_SIZE),
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.NUM_BANKS (NUM_BANKS),
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.WORD_SIZE (WORD_SIZE),
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.NUM_REQS (NUM_REQS)
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) cache_core_req_bank_sel (
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.core_req_valid (core_req_valid),
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.core_req_addr (core_req_addr),
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.core_req_ready (core_req_ready),
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.per_bank_valid (per_bank_valid),
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.per_bank_ready (per_bank_core_req_ready)
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);
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assign dram_req_tag = dram_req_addr;
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if (NUM_BANKS == 1) begin
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assign dram_rsp_ready = per_bank_dram_rsp_ready;
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end else begin
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assign dram_rsp_ready = per_bank_dram_rsp_ready[`DRAM_ADDR_BANK(dram_rsp_tag)];
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end
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for (genvar i = 0; i < NUM_BANKS; i++) begin
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wire [NUM_REQS-1:0] curr_bank_core_req_valid;
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wire [`CORE_REQ_TAG_COUNT-1:0] curr_bank_core_req_rw;
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wire [NUM_REQS-1:0][WORD_SIZE-1:0] curr_bank_core_req_byteen;
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wire [NUM_REQS-1:0][`WORD_ADDR_WIDTH-1:0] curr_bank_core_req_addr;
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wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] curr_bank_core_req_tag;
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wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] curr_bank_core_req_data;
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wire curr_bank_core_req_ready;
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wire curr_bank_core_rsp_valid;
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wire [`REQS_BITS-1:0] curr_bank_core_rsp_tid;
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wire [`WORD_WIDTH-1:0] curr_bank_core_rsp_data;
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wire [CORE_TAG_WIDTH-1:0] curr_bank_core_rsp_tag;
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wire curr_bank_core_rsp_ready;
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wire curr_bank_dram_req_valid;
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wire curr_bank_dram_req_rw;
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wire [BANK_LINE_SIZE-1:0] curr_bank_dram_req_byteen;
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wire [`LINE_ADDR_WIDTH-1:0] curr_bank_dram_req_addr;
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wire[`BANK_LINE_WIDTH-1:0] curr_bank_dram_req_data;
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wire curr_bank_dram_req_ready;
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wire curr_bank_dram_rsp_valid;
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wire [`BANK_LINE_WIDTH-1:0] curr_bank_dram_rsp_data;
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wire [`LINE_ADDR_WIDTH-1:0] curr_bank_dram_rsp_addr;
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wire curr_bank_dram_rsp_ready;
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wire curr_bank_snp_req_valid;
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wire [`LINE_ADDR_WIDTH-1:0] curr_bank_snp_req_addr;
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wire curr_bank_snp_req_inv;
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wire [SNP_TAG_WIDTH-1:0] curr_bank_snp_req_tag;
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wire curr_bank_snp_req_ready;
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wire curr_bank_snp_rsp_valid;
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wire [SNP_TAG_WIDTH-1:0] curr_bank_snp_rsp_tag;
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wire curr_bank_snp_rsp_ready;
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wire curr_bank_miss;
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// Core Req
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assign curr_bank_core_req_valid = (per_bank_valid[i] & {NUM_REQS{core_req_ready}});
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assign curr_bank_core_req_addr = core_req_addr;
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assign curr_bank_core_req_rw = core_req_rw;
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assign curr_bank_core_req_byteen = core_req_byteen;
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assign curr_bank_core_req_data = core_req_data;
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assign curr_bank_core_req_tag = core_req_tag;
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assign per_bank_core_req_ready[i] = curr_bank_core_req_ready;
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// Core WB
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assign curr_bank_core_rsp_ready = per_bank_core_rsp_ready[i];
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assign per_bank_core_rsp_valid [i] = curr_bank_core_rsp_valid;
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assign per_bank_core_rsp_tid [i] = curr_bank_core_rsp_tid;
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assign per_bank_core_rsp_tag [i] = curr_bank_core_rsp_tag;
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assign per_bank_core_rsp_data [i] = curr_bank_core_rsp_data;
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// DRAM request
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assign per_bank_dram_req_valid[i] = curr_bank_dram_req_valid;
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assign per_bank_dram_req_rw[i] = curr_bank_dram_req_rw;
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assign per_bank_dram_req_byteen[i] = curr_bank_dram_req_byteen;
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if (NUM_BANKS == 1) begin
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assign per_bank_dram_req_addr[i] = curr_bank_dram_req_addr;
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end else begin
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assign per_bank_dram_req_addr[i] = `LINE_TO_DRAM_ADDR(curr_bank_dram_req_addr, i);
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end
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assign per_bank_dram_req_data[i] = curr_bank_dram_req_data;
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assign curr_bank_dram_req_ready = per_bank_dram_req_ready[i];
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// DRAM response
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if (NUM_BANKS == 1) begin
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assign curr_bank_dram_rsp_valid = dram_rsp_valid;
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assign curr_bank_dram_rsp_addr = dram_rsp_tag;
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end else begin
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assign curr_bank_dram_rsp_valid = dram_rsp_valid && (`DRAM_ADDR_BANK(dram_rsp_tag) == i);
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assign curr_bank_dram_rsp_addr = `DRAM_TO_LINE_ADDR(dram_rsp_tag);
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end
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assign curr_bank_dram_rsp_data = dram_rsp_data;
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assign per_bank_dram_rsp_ready[i] = curr_bank_dram_rsp_ready;
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// Snoop request
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if (NUM_BANKS == 1) begin
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assign curr_bank_snp_req_valid = snp_req_valid;
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assign curr_bank_snp_req_addr = snp_req_addr;
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end else begin
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assign curr_bank_snp_req_valid = snp_req_valid && (`DRAM_ADDR_BANK(snp_req_addr) == i);
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assign curr_bank_snp_req_addr = `DRAM_TO_LINE_ADDR(snp_req_addr);
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end
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assign curr_bank_snp_req_inv = snp_req_inv;
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assign curr_bank_snp_req_tag = snp_req_tag;
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assign per_bank_snp_req_ready[i] = curr_bank_snp_req_ready;
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// Snoop response
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assign per_bank_snp_rsp_valid[i] = curr_bank_snp_rsp_valid;
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assign per_bank_snp_rsp_tag[i] = curr_bank_snp_rsp_tag;
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assign curr_bank_snp_rsp_ready = per_bank_snp_rsp_ready[i];
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//Misses
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assign per_bank_miss[i] = curr_bank_miss;
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VX_bank #(
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.BANK_ID (i),
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.CACHE_ID (CACHE_ID),
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.CACHE_SIZE (CACHE_SIZE),
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.BANK_LINE_SIZE (BANK_LINE_SIZE),
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.NUM_BANKS (NUM_BANKS),
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.WORD_SIZE (WORD_SIZE),
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.NUM_REQS (NUM_REQS),
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.CREQ_SIZE (CREQ_SIZE),
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.MSHR_SIZE (MSHR_SIZE),
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.DRFQ_SIZE (DRFQ_SIZE),
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.SNRQ_SIZE (SNRQ_SIZE),
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.CWBQ_SIZE (CWBQ_SIZE),
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.DREQ_SIZE (DREQ_SIZE),
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.SNPQ_SIZE (SNPQ_SIZE),
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.DRAM_ENABLE (DRAM_ENABLE),
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.FLUSH_ENABLE (FLUSH_ENABLE),
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.WRITE_ENABLE (WRITE_ENABLE),
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.CORE_TAG_WIDTH (CORE_TAG_WIDTH),
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.CORE_TAG_ID_BITS (CORE_TAG_ID_BITS),
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.SNP_TAG_WIDTH (SNP_TAG_WIDTH)
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) bank (
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`SCOPE_BIND_VX_cache_bank(i)
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.clk (clk),
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.reset (reset),
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// Core request
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.core_req_valid (curr_bank_core_req_valid),
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.core_req_rw (curr_bank_core_req_rw),
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.core_req_byteen (curr_bank_core_req_byteen),
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.core_req_addr (curr_bank_core_req_addr),
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.core_req_data (curr_bank_core_req_data),
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.core_req_tag (curr_bank_core_req_tag),
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.core_req_ready (curr_bank_core_req_ready),
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// Core response
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.core_rsp_valid (curr_bank_core_rsp_valid),
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.core_rsp_tid (curr_bank_core_rsp_tid),
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.core_rsp_data (curr_bank_core_rsp_data),
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.core_rsp_tag (curr_bank_core_rsp_tag),
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.core_rsp_ready (curr_bank_core_rsp_ready),
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// DRAM request
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.dram_req_valid (curr_bank_dram_req_valid),
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.dram_req_rw (curr_bank_dram_req_rw),
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.dram_req_byteen (curr_bank_dram_req_byteen),
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.dram_req_addr (curr_bank_dram_req_addr),
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.dram_req_data (curr_bank_dram_req_data),
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.dram_req_ready (curr_bank_dram_req_ready),
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// DRAM response
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.dram_rsp_valid (curr_bank_dram_rsp_valid),
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.dram_rsp_data (curr_bank_dram_rsp_data),
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.dram_rsp_addr (curr_bank_dram_rsp_addr),
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.dram_rsp_ready (curr_bank_dram_rsp_ready),
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// PERF: perf_msrq_stall
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`ifdef PERF_ENABLE
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.perf_msrq_stall (perf_msrq_stall_per_bank[i]),
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.perf_total_stall (perf_total_stall_per_bank[i]),
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.perf_evict (perf_evict_per_bank[i]),
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.perf_read_miss (perf_read_miss_per_bank[i]),
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.perf_write_miss (perf_write_miss_per_bank[i]),
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`endif
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// Snoop request
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.snp_req_valid (curr_bank_snp_req_valid),
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.snp_req_addr (curr_bank_snp_req_addr),
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.snp_req_inv (curr_bank_snp_req_inv),
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.snp_req_tag (curr_bank_snp_req_tag),
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.snp_req_ready (curr_bank_snp_req_ready),
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// Snoop response
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.snp_rsp_valid (curr_bank_snp_rsp_valid),
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.snp_rsp_tag (curr_bank_snp_rsp_tag),
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.snp_rsp_ready (curr_bank_snp_rsp_ready),
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//Misses
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.misses (curr_bank_miss)
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);
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end
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VX_cache_core_rsp_merge #(
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.NUM_BANKS (NUM_BANKS),
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.WORD_SIZE (WORD_SIZE),
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.NUM_REQS (NUM_REQS),
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.CORE_TAG_WIDTH (CORE_TAG_WIDTH),
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.CORE_TAG_ID_BITS (CORE_TAG_ID_BITS)
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) cache_core_rsp_merge (
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.clk (clk),
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.reset (reset),
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.per_bank_core_rsp_valid (per_bank_core_rsp_valid),
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.per_bank_core_rsp_tag (per_bank_core_rsp_tag),
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.per_bank_core_rsp_tid (per_bank_core_rsp_tid),
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.per_bank_core_rsp_data (per_bank_core_rsp_data),
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.per_bank_core_rsp_ready (per_bank_core_rsp_ready),
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.core_rsp_valid (core_rsp_valid),
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.core_rsp_tag (core_rsp_tag),
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.core_rsp_data (core_rsp_data),
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.core_rsp_ready (core_rsp_ready)
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);
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if (DRAM_ENABLE) begin
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wire [NUM_BANKS-1:0][(`DRAM_ADDR_WIDTH + 1 + BANK_LINE_SIZE + `BANK_LINE_WIDTH)-1:0] data_in;
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for (genvar i = 0; i < NUM_BANKS; i++) begin
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assign data_in[i] = {per_bank_dram_req_addr[i], per_bank_dram_req_rw[i], per_bank_dram_req_byteen[i], per_bank_dram_req_data[i]};
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end
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VX_stream_arbiter #(
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.NUM_REQS(NUM_BANKS),
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.DATAW(`DRAM_ADDR_WIDTH + 1 + BANK_LINE_SIZE + `BANK_LINE_WIDTH),
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.BUFFERED(NUM_BANKS >= 4)
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) dram_req_arb (
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.clk (clk),
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.reset (reset),
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.valid_in (per_bank_dram_req_valid),
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.data_in (data_in),
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.ready_in (per_bank_dram_req_ready),
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.valid_out (dram_req_valid),
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.data_out ({dram_req_addr, dram_req_rw, dram_req_byteen, dram_req_data}),
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.ready_out (dram_req_ready)
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);
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end else begin
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|
`UNUSED_VAR (per_bank_dram_req_valid)
|
|
`UNUSED_VAR (per_bank_dram_req_rw)
|
|
`UNUSED_VAR (per_bank_dram_req_byteen)
|
|
`UNUSED_VAR (per_bank_dram_req_addr)
|
|
`UNUSED_VAR (per_bank_dram_req_data)
|
|
assign per_bank_dram_req_ready = 0;
|
|
assign dram_req_valid = 0;
|
|
assign dram_req_rw = 0;
|
|
assign dram_req_byteen = 0;
|
|
assign dram_req_addr = 0;
|
|
assign dram_req_data = 0;
|
|
`UNUSED_VAR (dram_req_ready)
|
|
end
|
|
|
|
if (FLUSH_ENABLE) begin
|
|
VX_stream_arbiter #(
|
|
.NUM_REQS(NUM_BANKS),
|
|
.DATAW(SNP_TAG_WIDTH),
|
|
.BUFFERED(NUM_BANKS >= 4)
|
|
) snp_rsp_arb (
|
|
.clk (clk),
|
|
.reset (reset),
|
|
.valid_in (per_bank_snp_rsp_valid),
|
|
.data_in (per_bank_snp_rsp_tag),
|
|
.ready_in (per_bank_snp_rsp_ready),
|
|
.valid_out (snp_rsp_valid),
|
|
.data_out (snp_rsp_tag),
|
|
.ready_out (snp_rsp_ready)
|
|
);
|
|
end else begin
|
|
`UNUSED_VAR (per_bank_snp_rsp_valid)
|
|
`UNUSED_VAR (per_bank_snp_rsp_tag)
|
|
assign per_bank_snp_rsp_ready = 0;
|
|
assign snp_rsp_valid = 0;
|
|
assign snp_rsp_tag = 0;
|
|
`UNUSED_VAR (snp_rsp_ready)
|
|
end
|
|
|
|
`ifdef PERF_ENABLE
|
|
// per cycle: core_req_r, core_req_w
|
|
reg[($clog2(NUM_REQS+1)-1):0] perf_core_req_r_per_cycle, perf_core_req_w_per_cycle;
|
|
if (CORE_TAG_ID_BITS != 0) begin // core_req_rw is 1-bit wide
|
|
VX_countones #( // core_req_r
|
|
.N(NUM_REQS)
|
|
) perf_countones_core_req_r_count (
|
|
.valids (core_req_valid & {NUM_REQS{(~core_req_rw) & core_req_ready}}),
|
|
.count (perf_core_req_r_per_cycle)
|
|
);
|
|
VX_countones #( // core_req_w
|
|
.N(NUM_REQS)
|
|
) perf_countones_core_req_w_count (
|
|
.valids (core_req_valid & {NUM_REQS{(core_req_rw) & core_req_ready}}),
|
|
.count (perf_core_req_w_per_cycle)
|
|
);
|
|
end else begin // core_req_rw is NUM_REQS-bit wide
|
|
VX_countones #( // core_req_r
|
|
.N(NUM_REQS)
|
|
) perf_countones_core_req_r_count (
|
|
.valids (core_req_valid & (~core_req_rw) & {NUM_REQS{core_req_ready}}),
|
|
.count (perf_core_req_r_per_cycle)
|
|
);
|
|
VX_countones #( // core_req_w
|
|
.N(NUM_REQS)
|
|
) perf_countones_core_req_w_count (
|
|
.valids (core_req_valid & (core_req_rw) & {NUM_REQS{core_req_ready}}),
|
|
.count (perf_core_req_w_per_cycle)
|
|
);
|
|
end
|
|
// per cycle: dram_latency
|
|
reg[63:0] perf_dram_lat_per_cycle;
|
|
always@(posedge clk) begin
|
|
if(reset) begin
|
|
perf_dram_lat_per_cycle <= 0;
|
|
end else begin
|
|
if(dram_req_valid & (~dram_req_rw) & dram_req_ready & dram_rsp_valid & dram_rsp_ready) begin
|
|
perf_dram_lat_per_cycle <= perf_dram_lat_per_cycle;
|
|
end else if(dram_req_valid & (~dram_req_rw) & dram_req_ready) begin
|
|
perf_dram_lat_per_cycle <= perf_dram_lat_per_cycle + 64'd1;
|
|
end else if(dram_rsp_valid & dram_rsp_ready) begin
|
|
perf_dram_lat_per_cycle <= perf_dram_lat_per_cycle - 64'd1;
|
|
end
|
|
end
|
|
end
|
|
// per cycle: msrq stalls, total stalls, total eviction, read miss, write miss
|
|
reg [($clog2(NUM_BANKS+1)-1):0] perf_msrq_stall_per_cycle;
|
|
reg [($clog2(NUM_BANKS+1)-1):0] perf_total_stall_per_cycle;
|
|
reg [($clog2(NUM_BANKS+1)-1):0] perf_total_eviction_per_cycle;
|
|
reg [($clog2(NUM_BANKS+1)-1):0] perf_read_miss_per_cycle;
|
|
reg [($clog2(NUM_BANKS+1)-1):0] perf_write_miss_per_cycle;
|
|
VX_countones #(
|
|
.N(NUM_BANKS)
|
|
) perf_countones_msrq_stall_count (
|
|
.valids (perf_msrq_stall_per_bank),
|
|
.count (perf_msrq_stall_per_cycle)
|
|
);
|
|
VX_countones #(
|
|
.N(NUM_BANKS)
|
|
) perf_countones_total_stall_count (
|
|
.valids (perf_total_stall_per_bank),
|
|
.count (perf_total_stall_per_cycle)
|
|
);
|
|
VX_countones #(
|
|
.N(NUM_BANKS)
|
|
) perf_countones_total_evict_count (
|
|
.valids (perf_evict_per_bank),
|
|
.count (perf_total_eviction_per_cycle)
|
|
);
|
|
VX_countones #(
|
|
.N(NUM_BANKS)
|
|
) perf_countones_read_miss_count (
|
|
.valids (perf_read_miss_per_bank),
|
|
.count (perf_read_miss_per_cycle)
|
|
);
|
|
VX_countones #(
|
|
.N(NUM_BANKS)
|
|
) perf_countones_write_miss_count (
|
|
.valids (perf_write_miss_per_bank),
|
|
.count (perf_write_miss_per_cycle)
|
|
);
|
|
reg [63:0] perf_core_req_r, perf_core_req_w;
|
|
reg [63:0] perf_dram_lat, perf_dram_rsp;
|
|
reg [63:0] perf_msrq_stall;
|
|
reg [63:0] perf_total_stall;
|
|
reg [63:0] perf_total_eviction;
|
|
reg [63:0] perf_read_miss, perf_write_miss;
|
|
reg [63:0] perf_core_rsp_stall, perf_dram_stall;
|
|
always @ (posedge clk) begin
|
|
if (reset) begin
|
|
perf_core_req_r <= 0;
|
|
perf_core_req_w <= 0;
|
|
perf_dram_lat <= 0;
|
|
perf_dram_rsp <= 0;
|
|
perf_msrq_stall <= 0;
|
|
perf_total_stall <= 0;
|
|
perf_total_eviction <= 0;
|
|
perf_read_miss <= 0;
|
|
perf_write_miss <= 0;
|
|
perf_core_rsp_stall <= 0;
|
|
perf_dram_stall <= 0;
|
|
end else begin
|
|
// core_req_r, core_req_w
|
|
perf_core_req_r <= perf_core_req_r + $bits(perf_core_req_r)'(perf_core_req_r_per_cycle);
|
|
perf_core_req_w <= perf_core_req_w + $bits(perf_core_req_w)'(perf_core_req_w_per_cycle);
|
|
// dram_latency
|
|
perf_dram_lat <= perf_dram_lat + perf_dram_lat_per_cycle;
|
|
if (dram_rsp_valid & dram_rsp_ready) begin
|
|
perf_dram_rsp <= perf_dram_rsp + 64'd1;
|
|
end
|
|
// miss reserve queue stalls: bank->msrq_push_stall
|
|
perf_msrq_stall <= perf_msrq_stall + $bits(perf_msrq_stall)'(perf_msrq_stall_per_cycle);
|
|
// total stalls: from bank->pipeline_stall
|
|
perf_total_stall <= perf_total_stall + $bits(perf_total_stall)'(perf_total_stall_per_cycle);
|
|
// total eviction: from bank-> dwbq_push & do_writeback_st3 & !is_snp_st3
|
|
perf_total_eviction <= perf_total_eviction + $bits(perf_total_eviction)'(perf_total_eviction_per_cycle);
|
|
// read miss: from bank-> !pipeline_stall & miss_st1 & !is_msrq_st1 & !mem_rw_st1
|
|
perf_read_miss <= perf_read_miss + $bits(perf_read_miss)'(perf_read_miss_per_cycle);
|
|
// write miss: from bank-> !pipeline_stall & miss_st1 & !is_msrq_st1 & mem_rw_st1
|
|
perf_write_miss <= perf_write_miss + $bits(perf_write_miss)'(perf_write_miss_per_cycle);
|
|
// core_rsp_stall
|
|
if ((| core_rsp_valid) & !core_rsp_ready) begin
|
|
perf_core_rsp_stall <= perf_core_rsp_stall + 64'd1;
|
|
end
|
|
// dram_stall
|
|
if (dram_req_valid & !dram_req_ready) begin
|
|
perf_dram_stall <= perf_dram_stall + 64'd1;
|
|
end
|
|
end
|
|
end
|
|
assign perf_cache_if.total_read = perf_core_req_r;
|
|
assign perf_cache_if.total_write = perf_core_req_w;
|
|
assign perf_cache_if.dram_latency = perf_dram_lat;
|
|
assign perf_cache_if.dram_rsp = perf_dram_rsp;
|
|
assign perf_cache_if.msrq_stall = perf_msrq_stall;
|
|
assign perf_cache_if.total_stall = perf_total_stall;
|
|
assign perf_cache_if.total_eviction = perf_total_eviction;
|
|
assign perf_cache_if.read_miss = perf_read_miss;
|
|
assign perf_cache_if.write_miss = perf_write_miss;
|
|
assign perf_cache_if.core_rsp_stall = perf_core_rsp_stall;
|
|
assign perf_cache_if.dram_stall = perf_dram_stall;
|
|
|
|
`endif
|
|
|
|
endmodule
|