28 lines
728 B
Verilog
28 lines
728 B
Verilog
`include "VX_tex_define.vh"
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module VX_tex_stride #(
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parameter CORE_ID = 0
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) (
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input wire [`TEX_FORMAT_BITS-1:0] format,
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output wire [`TEX_STRIDE_BITS-1:0] log_stride
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);
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`UNUSED_PARAM (CORE_ID)
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reg [`TEX_STRIDE_BITS-1:0] log_stride_r;
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always @(*) begin
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case (format)
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`TEX_FORMAT_A8: log_stride_r = 0;
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`TEX_FORMAT_L8: log_stride_r = 0;
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`TEX_FORMAT_L8A8: log_stride_r = 1;
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`TEX_FORMAT_R5G6B5: log_stride_r = 1;
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`TEX_FORMAT_R4G4B4A4: log_stride_r = 1;
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// `TEX_FORMAT_R8G8B8A8
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default: log_stride_r = 2;
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endcase
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end
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assign log_stride = log_stride_r;
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endmodule
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