65 lines
2.6 KiB
Verilog
65 lines
2.6 KiB
Verilog
`include "VX_define.vh"
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module VX_scoreboard #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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VX_decode_if ibuf_deq_if,
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VX_writeback_if writeback_if,
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output wire delay
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);
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reg [`NUM_WARPS-1:0][`NUM_REGS-1:0] inuse_regs;
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wire [`NUM_REGS-1:0] deq_inuse_regs;
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assign deq_inuse_regs = inuse_regs[ibuf_deq_if.wid] & ibuf_deq_if.used_regs;
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assign delay = (| deq_inuse_regs);
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wire reserve_reg = ibuf_deq_if.valid && ibuf_deq_if.ready && (ibuf_deq_if.wb != 0);
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wire release_reg = writeback_if.valid && writeback_if.ready && writeback_if.eop;
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always @(posedge clk) begin
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if (reset) begin
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inuse_regs <= (`NUM_WARPS*`NUM_REGS)'(0);
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end else begin
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if (reserve_reg) begin
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inuse_regs[ibuf_deq_if.wid][ibuf_deq_if.rd] <= 1;
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end
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if (release_reg) begin
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inuse_regs[writeback_if.wid][writeback_if.rd] <= 0;
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assert(inuse_regs[writeback_if.wid][writeback_if.rd] != 0)
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else $error("%t: *** core%0d: invalid writeback register: wid=%0d, PC=%0h, rd=%0d",
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$time, CORE_ID, writeback_if.wid, writeback_if.PC, writeback_if.rd);
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end
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end
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end
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`ifdef DBG_PRINT_PIPELINE
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always @(posedge clk) begin
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if (ibuf_deq_if.valid && ~ibuf_deq_if.ready) begin
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$display("%t: *** core%0d-stall: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b",
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$time, CORE_ID, ibuf_deq_if.wid, ibuf_deq_if.PC, ibuf_deq_if.rd, ibuf_deq_if.wb,
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deq_inuse_regs[ibuf_deq_if.rd], deq_inuse_regs[ibuf_deq_if.rs1], deq_inuse_regs[ibuf_deq_if.rs2], deq_inuse_regs[ibuf_deq_if.rs3]);
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end
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end
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`endif
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reg [31:0] deadlock_ctr;
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wire [31:0] deadlock_timeout = 1000 * (10 ** (`L2_ENABLE + `L3_ENABLE));
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always @(posedge clk) begin
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if (reset) begin
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deadlock_ctr <= 0;
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end else if (ibuf_deq_if.valid && ~ibuf_deq_if.ready) begin
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deadlock_ctr <= deadlock_ctr + 1;
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assert(deadlock_ctr < deadlock_timeout) else $error("%t: *** core%0d-deadlock: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b",
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$time, CORE_ID, ibuf_deq_if.wid, ibuf_deq_if.PC, ibuf_deq_if.rd, ibuf_deq_if.wb,
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deq_inuse_regs[ibuf_deq_if.rd], deq_inuse_regs[ibuf_deq_if.rs1], deq_inuse_regs[ibuf_deq_if.rs2], deq_inuse_regs[ibuf_deq_if.rs3]);
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end else if (ibuf_deq_if.valid && ibuf_deq_if.ready) begin
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deadlock_ctr <= 0;
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end
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end
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endmodule |