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111cc294825b3f95aeff6e8c3ae4ae6094cec94c
vortex/hw/rtl
History
Blaise Tine 111cc29482 minor update
2021-02-04 15:28:04 -08:00
..
afu
lkg build rollout with 16cores optimization on arria10
2021-01-24 16:49:22 -08:00
cache
minor update
2021-02-04 15:28:04 -08:00
fp_cores
updating fdiv/fsqrt bram hex files, reset_delay updaet
2021-02-04 09:02:18 -08:00
interfaces
fixed GPR reset bug, fixed lsu dup loading, fixed riscv-tests
2021-01-11 23:55:09 -08:00
libs
updating fdiv/fsqrt bram hex files, reset_delay updaet
2021-02-04 09:02:18 -08:00
tex_unit
modelsim fixes && pipeline optimization
2020-07-28 14:20:23 -07:00
.DS_Store
project directories reorganization
2020-04-14 06:35:20 -04:00
.gitignore
fix opae build
2020-04-20 12:51:42 -07:00
Vortex.v
updating fdiv/fsqrt bram hex files, reset_delay updaet
2021-02-04 09:02:18 -08:00
VX_alu_unit.v
minor updates
2021-01-12 03:10:39 -08:00
VX_cluster.v
updating fdiv/fsqrt bram hex files, reset_delay updaet
2021-02-04 09:02:18 -08:00
VX_commit.v
minor updates
2021-01-12 15:19:38 -08:00
VX_config.vh
lkg build rollout with 16cores optimization on arria10
2021-01-24 16:49:22 -08:00
VX_core.v
added support for write-through cache, removed cache snooping support
2020-12-23 23:51:02 -08:00
VX_csr_arb.v
added support for write-through cache, removed cache snooping support
2020-12-23 23:51:02 -08:00
VX_csr_data.v
fixed GPR reset bug, fixed lsu dup loading, fixed riscv-tests
2021-01-11 23:55:09 -08:00
VX_csr_io_arb.v
lkg build rollout with 16cores optimization on arria10
2021-01-24 16:49:22 -08:00
VX_csr_unit.v
fixed loader script stack setup
2020-12-31 22:37:20 -05:00
VX_databus_arb.v
lkg build rollout with 16cores optimization on arria10
2021-01-24 16:49:22 -08:00
VX_decode.v
minor updates
2021-01-17 12:50:07 -08:00
VX_define.vh
specialized shared memory module
2021-01-16 04:41:58 -08:00
VX_execute.v
merging perf counters
2020-12-08 21:02:39 -08:00
VX_fetch.v
scope fixes
2020-10-13 08:44:55 -07:00
VX_fpu_unit.v
fcvt fix
2021-01-25 02:22:00 -08:00
VX_gpr_ram_f.v
minor update
2021-01-01 20:24:18 -08:00
VX_gpr_ram_i.v
fixed register file initialization to zero synthesis inference
2020-12-10 00:27:56 -08:00
VX_gpr_stage.v
fixed GPR reset bug, fixed lsu dup loading, fixed riscv-tests
2021-01-11 23:55:09 -08:00
VX_gpu_unit.v
scoreboard optimization - using writeback's end-of-packet status
2020-12-30 06:47:56 -08:00
VX_ibuffer.v
minor update - smem perf update
2021-02-01 10:29:20 -08:00
VX_icache_stage.v
cache optimization - moved read requests to stage1 and eliminating stage3
2020-12-31 07:40:58 -08:00
VX_instr_demux.v
lkg build rollout with 16cores optimization on arria10
2021-01-24 16:49:22 -08:00
VX_ipdom_stack.v
critical path optimization - fpga fmax @4c = ~212 mhz
2020-12-26 03:28:32 -08:00
VX_issue.v
minor updates
2021-01-12 15:19:38 -08:00
VX_lsu_unit.v
fcvt fix
2021-01-25 02:22:00 -08:00
VX_mem_arb.v
performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
2020-12-19 02:45:06 -08:00
VX_mem_unit.v
updating fdiv/fsqrt bram hex files, reset_delay updaet
2021-02-04 09:02:18 -08:00
VX_mul_unit.v
scoreboard optimization - using writeback's end-of-packet status
2020-12-30 06:47:56 -08:00
VX_pipeline.v
added support for write-through cache, removed cache snooping support
2020-12-23 23:51:02 -08:00
VX_platform.vh
lkg build rollout with 16cores optimization on arria10
2021-01-24 16:49:22 -08:00
VX_print_instr.vh
fixed GPR reset bug, fixed lsu dup loading, fixed riscv-tests
2021-01-11 23:55:09 -08:00
VX_scope.vh
ccip write fix
2021-01-14 22:49:06 -08:00
VX_scoreboard.v
lkg build rollout with 16cores optimization on arria10
2021-01-24 16:49:22 -08:00
VX_types.vh
FPU float<->int conversion optimization
2020-12-29 15:37:45 -08:00
VX_warp_sched.v
minor updates
2021-01-12 15:19:38 -08:00
VX_writeback.v
scoreboard optimization - using writeback's end-of-packet status
2020-12-30 06:47:56 -08:00