20 lines
502 B
Verilog
20 lines
502 B
Verilog
`include "VX_platform.vh"
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module VX_onehot_mux #(
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parameter DATAW = 1,
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parameter COUNT = 1
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) (
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input wire [COUNT-1:0][DATAW-1:0] data_in,
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input wire [COUNT-1:0] sel_in,
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output wire [DATAW-1:0] data_out
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);
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if (COUNT > 1) begin
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for (genvar i = 0; i < COUNT; ++i) begin
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assign data_out = sel_in[i] ? data_in[i] : 'z;
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end
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end else begin
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`UNUSED_VAR (sel_in)
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assign data_out = data_in;
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end
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endmodule |