24 lines
520 B
Verilog
24 lines
520 B
Verilog
`include "../VX_define.v"
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module VX_cache_bank_valid
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#(
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parameter NUMBER_BANKS = 0
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)
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(
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input wire [`NT_M1:0] i_p_valid,
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input wire [`NT_M1:0][31:0] i_p_addr,
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output reg [NUMBER_BANKS - 1 : 0][`NT_M1:0] thread_track_banks
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);
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generate
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integer t_id;
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always @(*) begin
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thread_track_banks = 0;
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for (t_id = 0; t_id <= `NT_M1; t_id = t_id + 1)
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begin
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thread_track_banks[i_p_addr[t_id][4:2]][t_id] = i_p_valid[t_id];
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end
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end
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endgenerate
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endmodule |