124 lines
4.4 KiB
Verilog
124 lines
4.4 KiB
Verilog
`include "VX_define.vh"
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module Vortex_axi #(
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parameter AXI_DATA_WIDTH = `VX_MEM_DATA_WIDTH,
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parameter AXI_ADDR_WIDTH = 32,
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parameter AXI_TID_WIDTH = `VX_MEM_TAG_WIDTH,
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localparam AXI_STROBE_WIDTH = (AXI_DATA_WIDTH / 8)
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)(
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// Clock
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input wire clk,
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input wire reset,
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// AXI write request
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output wire m_axi_wvalid,
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output wire m_axi_awvalid,
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output wire [AXI_TID_WIDTH-1:0] m_axi_awid,
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output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
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output wire [7:0] m_axi_awlen,
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output wire [2:0] m_axi_awsize,
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output wire [1:0] m_axi_awburst,
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output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata,
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output wire [AXI_STROBE_WIDTH-1:0] m_axi_wstrb,
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input wire m_axi_wready,
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input wire m_axi_awready,
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// AXI read request
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output wire m_axi_arvalid,
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output wire [AXI_TID_WIDTH-1:0] m_axi_arid,
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output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr,
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output wire [7:0] m_axi_arlen,
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output wire [2:0] m_axi_arsize,
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output wire [1:0] m_axi_arburst,
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input wire m_axi_arready,
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// AXI read response
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input wire m_axi_rvalid,
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input wire [AXI_TID_WIDTH-1:0] m_axi_rid,
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input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata,
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output wire m_axi_rready,
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// Status
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output wire busy
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);
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wire mem_req_valid;
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wire mem_req_rw;
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wire [`VX_MEM_BYTEEN_WIDTH-1:0] mem_req_byteen;
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wire [`VX_MEM_ADDR_WIDTH-1:0] mem_req_addr;
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wire [`VX_MEM_DATA_WIDTH-1:0] mem_req_data;
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wire [`VX_MEM_TAG_WIDTH-1:0] mem_req_tag;
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wire mem_req_ready;
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wire mem_rsp_valid;
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wire [`VX_MEM_DATA_WIDTH-1:0] mem_rsp_data;
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wire [`VX_MEM_TAG_WIDTH-1:0] mem_rsp_tag;
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wire mem_rsp_ready;
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VX_axi_adapter #(
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.VX_DATA_WIDTH (`VX_MEM_DATA_WIDTH),
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.VX_ADDR_WIDTH (`VX_MEM_ADDR_WIDTH),
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.VX_TAG_WIDTH (`VX_MEM_TAG_WIDTH),
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.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
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.AXI_ADDR_WIDTH (AXI_ADDR_WIDTH),
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.AXI_TID_WIDTH (AXI_TID_WIDTH)
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) axi_adapter (
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.mem_req_valid (mem_req_valid),
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.mem_req_rw (mem_req_rw),
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.mem_req_byteen (mem_req_byteen),
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.mem_req_addr (mem_req_addr),
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.mem_req_data (mem_req_data),
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.mem_req_tag (mem_req_tag),
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.mem_req_ready (mem_req_ready),
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.mem_rsp_valid (mem_rsp_valid),
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.mem_rsp_data (mem_rsp_data),
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.mem_rsp_tag (mem_rsp_tag),
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.mem_rsp_ready (mem_rsp_ready),
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.m_axi_wvalid (m_axi_wvalid),
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.m_axi_awvalid (m_axi_awvalid),
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.m_axi_awid (m_axi_awid),
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.m_axi_awaddr (m_axi_awaddr),
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.m_axi_awlen (m_axi_awlen),
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.m_axi_awsize (m_axi_awsize),
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.m_axi_awburst (m_axi_awburst),
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.m_axi_wdata (m_axi_wdata),
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.m_axi_wstrb (m_axi_wstrb),
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.m_axi_wready (m_axi_wready),
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.m_axi_awready (m_axi_awready),
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.m_axi_arvalid (m_axi_arvalid),
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.m_axi_arid (m_axi_arid),
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.m_axi_araddr (m_axi_araddr),
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.m_axi_arlen (m_axi_arlen),
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.m_axi_arsize (m_axi_arsize),
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.m_axi_arburst (m_axi_arburst),
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.m_axi_arready (m_axi_arready),
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.m_axi_rvalid (m_axi_rvalid),
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.m_axi_rid (m_axi_rid),
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.m_axi_rdata (m_axi_rdata),
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.m_axi_rready (m_axi_rready)
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);
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Vortex vortex (
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.clk (clk),
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.reset (reset),
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.mem_req_valid (mem_req_valid),
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.mem_req_rw (mem_req_rw),
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.mem_req_byteen (mem_req_byteen),
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.mem_req_addr (mem_req_addr),
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.mem_req_data (mem_req_data),
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.mem_req_tag (mem_req_tag),
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.mem_req_ready (mem_req_ready),
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.mem_rsp_valid (mem_rsp_valid),
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.mem_rsp_data (mem_rsp_data),
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.mem_rsp_tag (mem_rsp_tag),
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.mem_rsp_ready (mem_rsp_ready),
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.busy (busy)
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);
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endmodule |