c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
34 lines
647 B
Makefile
34 lines
647 B
Makefile
CXXFLAGS += -std=c++14 -Wall -Wextra -Wfatal-errors
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CXXFLAGS += -I../include -I../common -I../../hw -I$(XILINX_XRT)/include -I../../sim/common
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CXXFLAGS += -fPIC
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LDFLAGS += -shared -pthread
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LDFLAGS += -L$(XILINX_XRT)/lib -luuid -lxrt_coreutil
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SRCS = vortex.cpp ../common/utils.cpp ../../sim/common/util.cpp
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PROJECT = libvortex.so
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# Debugigng
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ifdef DEBUG
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CXXFLAGS += -g -O0
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else
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CXXFLAGS += -O2 -DNDEBUG
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endif
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# Enable scope logic analyzer
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ifdef SCOPE
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CXXFLAGS += -DSCOPE
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SRCS += ../common/scope.cpp
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endif
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all: $(PROJECT)
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$(PROJECT): $(SRCS) $(SCOPE_JSON)
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$(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@
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clean:
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rm -rf $(PROJECT) obj_dir
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