26 lines
807 B
Verilog
26 lines
807 B
Verilog
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`include "../VX_define.v"
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`ifndef VX_DRAM_REQ_RSP_INTER
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`define VX_DRAM_REQ_RSP_INTER
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interface VX_dram_req_rsp_inter ();
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// Req
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wire [31:0] o_m_evict_addr;
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wire [31:0] o_m_read_addr;
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wire o_m_valid;
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wire[`DCACHE_NUMBER_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata;
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wire o_m_read_or_write;
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// Rsp
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wire[`DCACHE_NUMBER_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata;
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wire i_m_ready;
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endinterface
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`endif
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