28 lines
582 B
Verilog
28 lines
582 B
Verilog
`include "VX_define.vh"
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module VX_generic_register #(
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parameter N,
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parameter PASSTHRU = 0
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) (
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input wire clk,
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input wire reset,
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input wire stall,
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input wire flush,
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input wire[N-1:0] in,
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output wire[N-1:0] out
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);
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reg [(N-1):0] value;
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always @(posedge clk) begin
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if (reset) begin
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value <= 0;
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end else if (flush) begin
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value <= 0;
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end else if (~stall) begin
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value <= in;
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end
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end
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assign out = PASSTHRU ? in : value;
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endmodule |