33 lines
1005 B
Verilog
33 lines
1005 B
Verilog
`include "VX_define.vh"
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module VX_gpr_ram (
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input wire clk,
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input wire [`NUM_THREADS-1:0] we,
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input wire [`NW_BITS+`NR_BITS-1:0] waddr,
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input wire [`NUM_THREADS-1:0][31:0] wdata,
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input wire [`NW_BITS+`NR_BITS-1:0] rs1,
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input wire [`NW_BITS+`NR_BITS-1:0] rs2,
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output wire [`NUM_THREADS-1:0][31:0] rs1_data,
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output wire [`NUM_THREADS-1:0][31:0] rs2_data
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);
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reg [`NUM_THREADS-1:0][3:0][7:0] mem [(`NUM_WARPS * `NUM_REGS)-1:0];
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reg [`NUM_THREADS-1:0][31:0] q1, q2;
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always @(posedge clk) begin
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for (integer i = 0; i < `NUM_THREADS; i++) begin
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if (we[i]) begin
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mem[waddr][i][0] <= wdata[i][07:00];
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mem[waddr][i][1] <= wdata[i][15:08];
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mem[waddr][i][2] <= wdata[i][23:16];
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mem[waddr][i][3] <= wdata[i][31:24];
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end
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end
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q1 <= mem[rs1];
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q2 <= mem[rs2];
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end
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assign rs1_data = q1;
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assign rs2_data = q2;
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endmodule |